[PATCH] D131436: [RISCV] Add {{$}} to some CHECK lines in MC tests.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: jrtc27, asb, luismarques, kito-cheng, reames.
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This adds {{$}} to most of the CHECK lines for errors about what
extension an instruction requires. This ensures we check all the
extensions when there is a list.

Some vector tests have been omitted because they need to be fixed.
I believe they were all floating point tests.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D131436

Files:
  llvm/test/MC/RISCV/priv-rv64-valid.s
  llvm/test/MC/RISCV/rv32c-invalid.s
  llvm/test/MC/RISCV/rv32c-only-valid.s
  llvm/test/MC/RISCV/rv32c-valid.s
  llvm/test/MC/RISCV/rv32dc-valid.s
  llvm/test/MC/RISCV/rv32f-invalid.s
  llvm/test/MC/RISCV/rv32fc-valid.s
  llvm/test/MC/RISCV/rv32i-aliases-invalid.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32m-invalid.s
  llvm/test/MC/RISCV/rv32zba-invalid.s
  llvm/test/MC/RISCV/rv32zbb-invalid.s
  llvm/test/MC/RISCV/rv32zbbp-invalid.s
  llvm/test/MC/RISCV/rv32zbe-invalid.s
  llvm/test/MC/RISCV/rv32zbf-invalid.s
  llvm/test/MC/RISCV/rv32zbkc-invalid.s
  llvm/test/MC/RISCV/rv32zbkx-invalid.s
  llvm/test/MC/RISCV/rv32zbp-invalid.s
  llvm/test/MC/RISCV/rv32zbr-invalid.s
  llvm/test/MC/RISCV/rv32zbt-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zfhmin-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zicbom-invalid.s
  llvm/test/MC/RISCV/rv32zicbop-invalid.s
  llvm/test/MC/RISCV/rv32zicboz-invalid.s
  llvm/test/MC/RISCV/rv32zmmul-invaild.s
  llvm/test/MC/RISCV/rv64a-valid.s
  llvm/test/MC/RISCV/rv64c-valid.s
  llvm/test/MC/RISCV/rv64d-valid.s
  llvm/test/MC/RISCV/rv64dc-valid.s
  llvm/test/MC/RISCV/rv64f-valid.s
  llvm/test/MC/RISCV/rv64i-aliases-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zfh-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zmmul-invalid.s
  llvm/test/MC/RISCV/rvv/add.s
  llvm/test/MC/RISCV/rvv/and.s
  llvm/test/MC/RISCV/rvv/clip.s
  llvm/test/MC/RISCV/rvv/compare.s
  llvm/test/MC/RISCV/rvv/div.s
  llvm/test/MC/RISCV/rvv/ext.s
  llvm/test/MC/RISCV/rvv/invalid-eew.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/macc.s
  llvm/test/MC/RISCV/rvv/mask.s
  llvm/test/MC/RISCV/rvv/minmax.s
  llvm/test/MC/RISCV/rvv/mul.s
  llvm/test/MC/RISCV/rvv/mv.s
  llvm/test/MC/RISCV/rvv/or.s
  llvm/test/MC/RISCV/rvv/others.s
  llvm/test/MC/RISCV/rvv/reduction.s
  llvm/test/MC/RISCV/rvv/shift.s
  llvm/test/MC/RISCV/rvv/store.s
  llvm/test/MC/RISCV/rvv/sub.s
  llvm/test/MC/RISCV/rvv/vsetvl.s
  llvm/test/MC/RISCV/rvv/xor.s

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