[PATCH] D124671: [AMDGPU] Do not raise wave priority beyond a specific number of VALU instructions.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp:127-128
+        break;
+      if (SIInstrInfo::isVMEM(MI) && MI.mayLoad())
+        LastVMEMLoad = &MI;
+      if (SIInstrInfo::isVALU(MI))
----------------
nhaehnle wrote:
> I believe NumVALUInsts should be reset to 0 here. It should probably also be reset at a number of other events, in particular DS instructions.
> 
> The reasoning is that we want to lower priority just before running a long dense block of VALU, so that other waves have a better chance of running address calculation VALU.
So would something like this work for the purpose?

```
      if (SIInstrInfo::isVALU(MI))
        ++NumVALUInsts;
      else
        NumVALUInsts = 0;
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124671/new/

https://reviews.llvm.org/D124671