[PATCH] D131380: [LoongArch] Support register-register-addressed GPR loads/stores

[Ray Wang via Phabricator via llvm-commits]

wangleiat added inline comments.


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Comment at: llvm/lib/Target/LoongArch/LoongArchInstrInfo.td:865
+class RegRegLdPat<PatFrag LoadOp, LAInst Inst>
+  : Pat<(GRLenVT (LoadOp (AddLike BaseAddr:$rj, GPR:$rk))),
+        (Inst BaseAddr:$rj, GPR:$rk)>;
----------------
Only for LA64 i64 is ok, GRLenVT will increase isel table size.


================
Comment at: llvm/lib/Target/LoongArch/LoongArchInstrInfo.td:865
+class RegRegLdPat<PatFrag LoadOp, LAInst Inst>
+  : Pat<(GRLenVT (LoadOp (AddLike BaseAddr:$rj, GPR:$rk))),
+        (Inst BaseAddr:$rj, GPR:$rk)>;
----------------
wangleiat wrote:
> Only for LA64 i64 is ok, GRLenVT will increase isel table size.
AddLike-> add


================
Comment at: llvm/lib/Target/LoongArch/LoongArchInstrInfo.td:900
+class RegRegStPat<PatFrag StoreOp, LAInst Inst, RegisterClass StTy>
+  : Pat<(StoreOp (GRLenVT StTy:$rd), (AddLike BaseAddr:$rj, GPR:$rk)),
+        (Inst StTy:$rd, BaseAddr:$rj, GPR:$rk)>;
----------------
ditto


================
Comment at: llvm/lib/Target/LoongArch/LoongArchInstrInfo.td:900
+class RegRegStPat<PatFrag StoreOp, LAInst Inst, RegisterClass StTy>
+  : Pat<(StoreOp (GRLenVT StTy:$rd), (AddLike BaseAddr:$rj, GPR:$rk)),
+        (Inst StTy:$rd, BaseAddr:$rj, GPR:$rk)>;
----------------
wangleiat wrote:
> ditto
ditto


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131380/new/

https://reviews.llvm.org/D131380