[PATCH] D131379: [RISCV] Add ReadFStoreData as a SchedRead.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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The floating point stores use a different register class, it
probably makes sense to have a different SchedRead.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D131379

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVSchedRocket.td
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/lib/Target/RISCV/RISCVSchedule.td


Index: llvm/lib/Target/RISCV/RISCVSchedule.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSchedule.td
+++ llvm/lib/Target/RISCV/RISCVSchedule.td
@@ -112,6 +112,7 @@
 def ReadMemBase     : SchedRead;
 def ReadFMemBase    : SchedRead;
 def ReadStoreData   : SchedRead;
+def ReadFStoreData  : SchedRead;
 def ReadIALU        : SchedRead;
 def ReadIALU32      : SchedRead;    // 32-bit integer ALU operations on RV64I
 def ReadShiftImm    : SchedRead;
Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -188,6 +188,7 @@
 def : ReadAdvance<ReadAtomicLDD, 0>;
 def : ReadAdvance<ReadAtomicSTW, 0>;
 def : ReadAdvance<ReadAtomicSTD, 0>;
+def : ReadAdvance<ReadFStoreData, 0>;
 def : ReadAdvance<ReadFMemBase, 0>;
 def : ReadAdvance<ReadFALU32, 0>;
 def : ReadAdvance<ReadFALU64, 0>;
Index: llvm/lib/Target/RISCV/RISCVSchedRocket.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -201,6 +201,7 @@
 def : ReadAdvance<ReadAtomicLDD, 0>;
 def : ReadAdvance<ReadAtomicSTW, 0>;
 def : ReadAdvance<ReadAtomicSTD, 0>;
+def : ReadAdvance<ReadFStoreData, 0>;
 def : ReadAdvance<ReadFMemBase, 0>;
 def : ReadAdvance<ReadFALU32, 0>;
 def : ReadAdvance<ReadFALU64, 0>;
Index: llvm/lib/Target/RISCV/RISCVInstrInfoF.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -160,7 +160,7 @@
     : RVInstS<funct3, OPC_STORE_FP, (outs),
               (ins rty:$rs2, GPR:$rs1, simm12:$imm12),
               opcodestr, "$rs2, ${imm12}(${rs1})">,
-      Sched<[sw, ReadStoreData, ReadFMemBase]>;
+      Sched<[sw, ReadFStoreData, ReadFMemBase]>;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1,
     UseNamedOperandTable = 1, hasPostISelHook = 1, isCommutable = 1 in


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