[PATCH] D131340: [RISC-V][HWASAN] Add intrinsics required for HWASAN support for RISC-V

[Alexey Baturo via Phabricator via llvm-commits]

smd added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:149
 
+def GPRNoX1X6X7X28X29X30X31 : RegisterClass<"RISCV", [XLenVT], 32, (sub GPR, X1, X6, X7, X28, X29, X30, X31)> {
+  let RegInfos = XLenRI;
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craig.topper wrote:
> I think this line probably exceeds 80 characters
Fixed, thanks


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131340/new/

https://reviews.llvm.org/D131340