[compiler-rt] ace6e17 - [RISCV] Support fe_getround and fe_raise_inexact in builtins

[via llvm-commits]

Author: luxufan
Date: 2022-08-08T09:58:27+08:00
New Revision: ace6e172bd2c86a3b035b90c7e4adedb6ab7a291

URL: https://github.com/llvm/llvm-project/commit/ace6e172bd2c86a3b035b90c7e4adedb6ab7a291
DIFF: https://github.com/llvm/llvm-project/commit/ace6e172bd2c86a3b035b90c7e4adedb6ab7a291.diff

LOG: [RISCV] Support fe_getround and fe_raise_inexact in builtins

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D128240

Added: 
    compiler-rt/lib/builtins/riscv/fp_mode.c

Modified: 
    compiler-rt/lib/builtins/CMakeLists.txt

Removed: 
    


################################################################################
diff  --git a/compiler-rt/lib/builtins/CMakeLists.txt b/compiler-rt/lib/builtins/CMakeLists.txt
index 795fe2ab316d8..6143457cc9339 100644
--- a/compiler-rt/lib/builtins/CMakeLists.txt
+++ b/compiler-rt/lib/builtins/CMakeLists.txt
@@ -650,6 +650,7 @@ endif()
 set(powerpc64le_SOURCES ${powerpc64_SOURCES})
 
 set(riscv_SOURCES
+  riscv/fp_mode.c
   riscv/save.S
   riscv/restore.S
   ${GENERIC_SOURCES}

diff  --git a/compiler-rt/lib/builtins/riscv/fp_mode.c b/compiler-rt/lib/builtins/riscv/fp_mode.c
new file mode 100644
index 0000000000000..c542c34c9cc8c
--- /dev/null
+++ b/compiler-rt/lib/builtins/riscv/fp_mode.c
@@ -0,0 +1,42 @@
+//=== lib/builtins/riscv/fp_mode.c - Floaing-point mode utilities -*- C -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+#include "../fp_mode.h"
+
+#define RISCV_TONEAREST  0x0
+#define RISCV_TOWARDZERO 0x1
+#define RISCV_DOWNWARD   0x2
+#define RISCV_UPWARD     0x3
+
+#define RISCV_INEXACT    0x1
+
+CRT_FE_ROUND_MODE __fe_getround(void) {
+#if defined(__riscv_f)
+  int frm;
+  __asm__ __volatile__("frrm %0" : "=r" (frm));
+  switch (frm) {
+    case RISCV_TOWARDZERO:
+      return CRT_FE_TOWARDZERO;
+    case RISCV_DOWNWARD:
+      return CRT_FE_DOWNWARD;
+    case RISCV_UPWARD:
+      return CRT_FE_UPWARD;
+    case RISCV_TONEAREST:
+    default:
+      return CRT_FE_TONEAREST;
+  }
+#else
+  return CRT_FE_TONEAREST;
+#endif
+}
+
+int __fe_raise_inexact(void) {
+#if defined(__riscv_f)
+  __asm__ __volatile__("csrsi fflags, %0" :: "i" (RISCV_INEXACT));
+#endif
+  return 0;
+}