[PATCH] D131343: [RISC-V][HWASAN] Add support for HWASAN code instrumentation for RISC-V

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Aug 7 12:09:24 PDT 2022


craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp:264
+  assert(TT.isOSBinFormatELF());
+  std::unique_ptr<MCSubtargetInfo> STI(
+      TM.getTarget().createMCSubtargetInfo(TT.str(), "", ""));
----------------
Why do we need to create STI when there's already an STI as a member of this class?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131343/new/

https://reviews.llvm.org/D131343



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