[PATCH] D131340: [RISC-V][HWASAN] Add intrinsics required for HWASAN support for RISC-V

[Alexey Baturo via Phabricator via llvm-commits]

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[2/7] patch series to port HWASAN for riscv64

Depends On D131339 <https://reviews.llvm.org/D131339>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D131340

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td


Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -146,6 +146,10 @@
   let RegInfos = XLenRI;
 }
 
+def GPRNoX1X6X7X28X29X30X31 : RegisterClass<"RISCV", [XLenVT], 32, (sub GPR, X1, X6, X7, X28, X29, X30, X31)> {
+  let RegInfos = XLenRI;
+}
+
 // Don't use X1 or X5 for JALR since that is a hint to pop the return address
 // stack on some microarchitectures. Also remove the reserved registers X0, X2,
 // X3, and X4 as it reduces the number of register classes that get synthesized
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1675,6 +1675,15 @@
 // debugger if possible.
 def : Pat<(debugtrap), (EBREAK)>;
 
+let Predicates = [IsRV64], Uses = [ X5 ],
+                           Defs = [ X1, X6, X7, X28, X29, X30, X31 ] in {
+def HWASAN_CHECK_MEMACCESS_SHORTGRANULES : Pseudo<
+  (outs), (ins GPRNoX1X6X7X28X29X30X31:$ptr, i32imm:$accessinfo),
+  [(int_hwasan_check_memaccess_shortgranules X5,
+                                             GPRNoX1X6X7X28X29X30X31:$ptr,
+                                             (i32 timm:$accessinfo))]>;
+}
+
 /// Simple optimization
 def : Pat<(add GPR:$rs1, (AddiPair:$rs2)),
           (ADDI (ADDI GPR:$rs1, (AddiPairImmLarge AddiPair:$rs2)),


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