[PATCH] D131339: [RISC-V] Add explicit check for risc-v 32/64 bit triples

[Alexey Baturo via Phabricator via llvm-commits]

smd created this revision.
Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, luismarques, sameer.abuasal, s.egerton, Jim, PkmX, rogfer01, shiva0217, kito-cheng, simoncook, arichardson.
Herald added a project: All.
smd added reviewers: eugenis, vitalybuka, luismarques, kito-cheng.
smd retitled this revision from "[RISC-V][HWASAN] Add intrinsics required for HWASAN support for RISC-V" to "[RISC-V] Add explicit check for risc-v 32/64 bit triples".
smd added a project: Sanitizers.
smd published this revision for review.
Herald added subscribers: llvm-commits, pcwang-thead.
Herald added a project: LLVM.

[1/7] patch series to port ASAN for riscv64


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D131339

Files:
  llvm/include/llvm/ADT/Triple.h


Index: llvm/include/llvm/ADT/Triple.h
===================================================================
--- llvm/include/llvm/ADT/Triple.h
+++ llvm/include/llvm/ADT/Triple.h
@@ -859,10 +859,14 @@
     return getArch() == Triple::ppc64 || getArch() == Triple::ppc64le;
   }
 
+  /// Tests whether the target is RISC-V 32-bit.
+  bool isRISCV32() const { return getArch() == Triple::riscv32; }
+
+  /// Tests whether the target is RISC-V 64-bit.
+  bool isRISCV64() const { return getArch() == Triple::riscv64; }
+
   /// Tests whether the target is RISC-V (32- and 64-bit).
-  bool isRISCV() const {
-    return getArch() == Triple::riscv32 || getArch() == Triple::riscv64;
-  }
+  bool isRISCV() const { return isRISCV32() || isRISCV64(); }
 
   /// Tests whether the target is 32-bit SPARC (little and big endian).
   bool isSPARC32() const {


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