[PATCH] D131350: [DAG] Ensure Legal BUILD_VECTOR elements types in shuffle->And combine

[Dave Green via Phabricator via llvm-commits]

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D129150 <https://reviews.llvm.org/D129150> added a combine from shuffles to And that creates a BUILD_VECTOR of constant elements. We need to ensure that the elements are of a legal type, to prevent asserts during lowering.

Fixes #56970.


https://reviews.llvm.org/D131350

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/ARM/vector-store.ll


Index: llvm/test/CodeGen/ARM/vector-store.ll
===================================================================
--- llvm/test/CodeGen/ARM/vector-store.ll
+++ llvm/test/CodeGen/ARM/vector-store.ll
@@ -397,3 +397,24 @@
   %next = getelementptr <4 x i32>, <4 x i32>* %ptr.out, i32 2
   ret <4 x i32>* %next
 }
+
+define void @v3i8store(<3 x i8> *%p) {
+; CHECK-LABEL: v3i8store:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    sub sp, #4
+; CHECK-NEXT:    vmov.i32 d16, #0xff
+; CHECK-NEXT:    mov r1, sp
+; CHECK-NEXT:    vmov.i32 d17, #0x0
+; CHECK-NEXT:    movs r2, #0
+; CHECK-NEXT:    vand d16, d17, d16
+; CHECK-NEXT:    vst1.32 {d16[0]}, [r1:32]
+; CHECK-NEXT:    vld1.32 {d16[0]}, [r1:32]
+; CHECK-NEXT:    vmovl.u16 q8, d16
+; CHECK-NEXT:    strb r2, [r0, #2]
+; CHECK-NEXT:    vmov.32 r1, d16[0]
+; CHECK-NEXT:    strh r1, [r0]
+; CHECK-NEXT:    add sp, #4
+; CHECK-NEXT:    bx lr
+  store <3 x i8> zeroinitializer, <3 x i8> *%p, align 4
+  ret void
+}
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -22748,6 +22748,7 @@
       SDLoc DL(N);
       EVT IntVT = VT.changeVectorElementTypeToInteger();
       EVT IntSVT = VT.getVectorElementType().changeTypeToInteger();
+      IntSVT = TLI.getTypeToTransformTo(*DAG.getContext(), IntSVT);
       SDValue ZeroElt = DAG.getConstant(0, DL, IntSVT);
       SDValue AllOnesElt = DAG.getAllOnesConstant(DL, IntSVT);
       SmallVector<SDValue, 16> AndMask(NumElts, DAG.getUNDEF(IntSVT));


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