[llvm] ef60e44 - [PowerPC] fix stack size allocated for float point argument

[Chen Zheng via llvm-commits]

Author: Chen Zheng
Date: 2022-08-06T08:38:52-04:00
New Revision: ef60e44fe874e28a6cfff57533b63c752a36e7dd

URL: https://github.com/llvm/llvm-project/commit/ef60e44fe874e28a6cfff57533b63c752a36e7dd
DIFF: https://github.com/llvm/llvm-project/commit/ef60e44fe874e28a6cfff57533b63c752a36e7dd.diff

LOG: [PowerPC] fix stack size allocated for float point argument

This is for https://github.com/llvm/llvm-project/issues/56469

Allocate 4 bytes for float point arguments on PPC32.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D129558

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCCallingConv.td
    llvm/test/CodeGen/PowerPC/fminnum.ll
    llvm/test/CodeGen/PowerPC/pr56469.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/PowerPC/PPCCallingConv.td b/llvm/lib/Target/PowerPC/PPCCallingConv.td
index 1901e8d1ebf10..3df31774f5aa4 100644
--- a/llvm/lib/Target/PowerPC/PPCCallingConv.td
+++ b/llvm/lib/Target/PowerPC/PPCCallingConv.td
@@ -206,13 +206,8 @@ def CC_PPC32_SVR4_Common : CallingConv<[
   
   CCIfType<[i32], CCAssignToStack<4, 4>>,
   
-  // Floats are stored in double precision format, thus they have the same
-  // alignment and size as doubles.
-  // With SPE floats are stored as single precision, so have alignment and
-  // size of int.
-  CCIfType<[f32,f64], CCIfNotSubtarget<"hasSPE()", CCAssignToStack<8, 8>>>,
-  CCIfType<[f32], CCIfSubtarget<"hasSPE()", CCAssignToStack<4, 4>>>,
-  CCIfType<[f64], CCIfSubtarget<"hasSPE()", CCAssignToStack<8, 8>>>,
+  CCIfType<[f32], CCAssignToStack<4, 4>>,
+  CCIfType<[f64], CCAssignToStack<8, 8>>,
 
   // Vectors and float128 get 16-byte stack slots that are 16-byte aligned.
   CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>,

diff  --git a/llvm/test/CodeGen/PowerPC/fminnum.ll b/llvm/test/CodeGen/PowerPC/fminnum.ll
index c4788a6001c78..18db085a48376 100644
--- a/llvm/test/CodeGen/PowerPC/fminnum.ll
+++ b/llvm/test/CodeGen/PowerPC/fminnum.ll
@@ -328,13 +328,13 @@ define <8 x float> @test_intrinsic_fmin_v8f32(<8 x float> %x, <8 x float> %y) {
 ; CHECK-NEXT:    fmr 30, 7
 ; CHECK-NEXT:    stfd 31, 120(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    fmr 31, 8
-; CHECK-NEXT:    lfs 24, 192(1)
-; CHECK-NEXT:    lfs 23, 184(1)
-; CHECK-NEXT:    lfs 22, 176(1)
-; CHECK-NEXT:    lfs 21, 168(1)
-; CHECK-NEXT:    lfs 20, 160(1)
-; CHECK-NEXT:    lfs 19, 152(1)
-; CHECK-NEXT:    lfs 18, 144(1)
+; CHECK-NEXT:    lfs 24, 164(1)
+; CHECK-NEXT:    lfs 23, 160(1)
+; CHECK-NEXT:    lfs 22, 156(1)
+; CHECK-NEXT:    lfs 21, 152(1)
+; CHECK-NEXT:    lfs 20, 148(1)
+; CHECK-NEXT:    lfs 19, 144(1)
+; CHECK-NEXT:    lfs 18, 140(1)
 ; CHECK-NEXT:    bl fminf
 ; CHECK-NEXT:    fmr 17, 1
 ; CHECK-NEXT:    fmr 1, 25

diff  --git a/llvm/test/CodeGen/PowerPC/pr56469.ll b/llvm/test/CodeGen/PowerPC/pr56469.ll
index 4ce2ad39cde87..a1865de80cf77 100644
--- a/llvm/test/CodeGen/PowerPC/pr56469.ll
+++ b/llvm/test/CodeGen/PowerPC/pr56469.ll
@@ -11,11 +11,11 @@ define void @callee(float  %a, float  %b, float  %c, float  %d, float  %e, float
 ; CHECK-NEXT:    stwu 1, -16(1)
 ; CHECK-NEXT:    lfs 1, 24(1)
 ; CHECK-NEXT:    lis 3, .L.str at ha
-; CHECK-NEXT:    lfs 2, 32(1)
+; CHECK-NEXT:    lfs 2, 28(1)
 ; CHECK-NEXT:    la 3, .L.str at l(3)
-; CHECK-NEXT:    lfs 3, 40(1)
+; CHECK-NEXT:    lfs 3, 32(1)
 ; CHECK-NEXT:    creqv 6, 6, 6
-; CHECK-NEXT:    lfs 4, 48(1)
+; CHECK-NEXT:    lfs 4, 36(1)
 ; CHECK-NEXT:    bl printf
 ; CHECK-NEXT:    lwz 0, 20(1)
 ; CHECK-NEXT:    addi 1, 1, 16