[PATCH] D131260: [DAG] select Cond, C, -1 --> or (sext Cond), C if Cond is MVT::i1

[Amaury SECHET via Phabricator via llvm-commits]

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This seems to be beneficial overall, except for midpoint-int.ll .

The X86 backend seems to generate zeroing that are not necesary.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D131260

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/PowerPC/ppc32-selectcc-i64.ll
  llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
  llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
  llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
  llvm/test/CodeGen/X86/memcmp-optsize-x32.ll
  llvm/test/CodeGen/X86/memcmp-optsize.ll
  llvm/test/CodeGen/X86/memcmp-pgso-x32.ll
  llvm/test/CodeGen/X86/memcmp-pgso.ll
  llvm/test/CodeGen/X86/memcmp-x32.ll
  llvm/test/CodeGen/X86/memcmp.ll
  llvm/test/CodeGen/X86/midpoint-int.ll
  llvm/test/CodeGen/X86/select.ll
  llvm/test/CodeGen/X86/select_const.ll

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