[llvm] 19bb535 - [AMDGPU] Remove unused MIMG tablegen variants
Mirko Brkusanin via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 5 06:55:29 PDT 2022
Author: Mirko Brkusanin
Date: 2022-08-05T15:30:47+02:00
New Revision: 19bb535ed99407c95863807a01bc11e205842070
URL: https://github.com/llvm/llvm-project/commit/19bb535ed99407c95863807a01bc11e205842070
DIFF: https://github.com/llvm/llvm-project/commit/19bb535ed99407c95863807a01bc11e205842070.diff
LOG: [AMDGPU] Remove unused MIMG tablegen variants
There are no AMDGPUSampleVariant versions for _G16, it is treated more like a
modifier for derivatives (_D) (also for intrinsics where it is overloaded type
instead of part of instrinsic name) so we ended up making more variants for
these instruction then we actually needed.
32-bit derivatives need 6 dwords at most, while 16-bit need 4 at most. Using
same AMDGPUSampleVariant for both, we ended up creating 2 extra variants per
instruction than were necessary.
In total this deletes 260 unused tablegen records.
Differential Revision: https://reviews.llvm.org/D131252
Added:
Modified:
llvm/lib/Target/AMDGPU/MIMGInstructions.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index 97c0c9223c69c..19eb39e063840 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -981,15 +981,19 @@ class MIMGAddrSizes_dw_range<list<int> range> {
int Max = !if(!empty(!tail(range)), Min, !head(!tail(range)));
}
-class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> {
+class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample, bit isG16> {
// List of all possible numbers of address words, taking all combinations of
// A16 and image dimension into account (note: no MSAA, since this is for
// sample/gather ops).
list<int> AllNumAddrWords =
!foreach(dw, !if(sample.Gradients,
- !if(!eq(sample.LodOrClamp, ""),
- [2, 3, 4, 5, 6, 7, 8, 9],
- [2, 3, 4, 5, 6, 7, 8, 9, 10]),
+ !if(isG16,
+ !if(!eq(sample.LodOrClamp, ""),
+ [2, 3, 4, 5, 6, 7],
+ [2, 3, 4, 5, 6, 7, 8]),
+ !if(!eq(sample.LodOrClamp, ""),
+ [2, 3, 4, 5, 6, 7, 8, 9],
+ [2, 3, 4, 5, 6, 7, 8, 9, 10])),
!if(!eq(sample.LodOrClamp, ""),
[1, 2, 3],
[1, 2, 3, 4])),
@@ -1028,8 +1032,8 @@ class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> {
multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm,
AMDGPUSampleVariant sample, RegisterClass dst_rc,
bit enableDisasm = 0,
- bit ExtendedImageInst = 1> {
- foreach addr = MIMG_Sampler_AddrSizes<sample>.MachineInstrs in {
+ bit ExtendedImageInst = 1, bit isG16 = 0> {
+ foreach addr = MIMG_Sampler_AddrSizes<sample, isG16>.MachineInstrs in {
let VAddrDwords = addr.NumWords in {
if op.HAS_GFX10M then {
def _V # addr.NumWords
@@ -1051,7 +1055,7 @@ multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm,
}
}
- foreach addr = MIMG_Sampler_AddrSizes<sample>.NSAInstrs in {
+ foreach addr = MIMG_Sampler_AddrSizes<sample, isG16>.NSAInstrs in {
let VAddrDwords = addr.NumWords in {
if op.HAS_GFX10M then {
def _V # addr.NumWords # _nsa_gfx10
@@ -1087,15 +1091,15 @@ multiclass MIMG_Sampler <mimgopc op, AMDGPUSampleVariant sample, bit wqm = 0,
let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm,
mayLoad = !not(isGetLod) in {
let VDataDwords = 1 in
- defm _V1 : MIMG_Sampler_Src_Helper<op, asm, sample, VGPR_32, 1, ExtendedImageInst>;
+ defm _V1 : MIMG_Sampler_Src_Helper<op, asm, sample, VGPR_32, 1, ExtendedImageInst, isG16>;
let VDataDwords = 2 in
- defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64, 0, ExtendedImageInst>;
+ defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64, 0, ExtendedImageInst, isG16>;
let VDataDwords = 3 in
- defm _V3 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_96, 0, ExtendedImageInst>;
+ defm _V3 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_96, 0, ExtendedImageInst, isG16>;
let VDataDwords = 4 in
- defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 0, ExtendedImageInst>;
+ defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 0, ExtendedImageInst, isG16>;
let VDataDwords = 5 in
- defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160, 0, ExtendedImageInst>;
+ defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160, 0, ExtendedImageInst, isG16>;
}
}
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