[PATCH] D131254: [AMDGPU][GISel] Enable Selection of ADD3 for G_PTR_ADD

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:3438-3451
+    dbgs() << "  Looking to transform G_PTR_ADD\n";
+    MachineIRBuilder MIB(I);
+
+    Register DstReg = I.getOperand(0).getReg();
+    Register AddOp1Reg = I.getOperand(1).getReg();
+    const LLT PtrTy = MRI.getType(DstReg);
+
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I'd prefer to avoid pre-hacking the MIR or introducing new instructions here and have tablegen handle everything


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131254/new/

https://reviews.llvm.org/D131254