[llvm] 1bd31a6 - [NFC] Add SmallVector constructor to allow creation of SmallVector<T> from ArrayRef of items convertible to type T
Dawid Jurczak via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 5 04:38:43 PDT 2022
Author: Dawid Jurczak
Date: 2022-08-05T13:35:41+02:00
New Revision: 1bd31a689844a43c9cde41a067119bef11159539
URL: https://github.com/llvm/llvm-project/commit/1bd31a689844a43c9cde41a067119bef11159539
DIFF: https://github.com/llvm/llvm-project/commit/1bd31a689844a43c9cde41a067119bef11159539.diff
LOG: [NFC] Add SmallVector constructor to allow creation of SmallVector<T> from ArrayRef of items convertible to type T
Extracted from https://reviews.llvm.org/D129781 and address comment:
https://reviews.llvm.org/D129781#3655571
Differential Revision: https://reviews.llvm.org/D130268
Added:
Modified:
llvm/include/llvm/ADT/SmallVector.h
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
llvm/unittests/ADT/SmallVectorTest.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/ADT/SmallVector.h b/llvm/include/llvm/ADT/SmallVector.h
index 83ef0ab3902d1..9a127552c5499 100644
--- a/llvm/include/llvm/ADT/SmallVector.h
+++ b/llvm/include/llvm/ADT/SmallVector.h
@@ -32,6 +32,8 @@
namespace llvm {
+template <typename T> class ArrayRef;
+
template <typename IteratorT> class iterator_range;
template <class Iterator>
@@ -1208,6 +1210,12 @@ class LLVM_GSL_OWNER SmallVector : public SmallVectorImpl<T>,
this->append(IL);
}
+ template <typename U,
+ typename = std::enable_if_t<std::is_convertible<U, T>::value>>
+ explicit SmallVector(ArrayRef<U> A) : SmallVectorImpl<T>(N) {
+ this->append(A.begin(), A.end());
+ }
+
SmallVector(const SmallVector &RHS) : SmallVectorImpl<T>(N) {
if (!RHS.empty())
SmallVectorImpl<T>::operator=(RHS);
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 0723899164958..1a37c45de7c4b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -19421,7 +19421,7 @@ SDValue DAGCombiner::combineInsertEltToShuffle(SDNode *N, unsigned InsIndex) {
}
if (ElementOffset != -1) {
- SmallVector<int, 16> NewMask(Mask.begin(), Mask.end());
+ SmallVector<int, 16> NewMask(Mask);
auto *ExtrIndex = cast<ConstantSDNode>(InsertVal.getOperand(1));
NewMask[InsIndex] = ElementOffset + ExtrIndex->getZExtValue();
@@ -22401,7 +22401,7 @@ static SDValue replaceShuffleOfInsert(ShuffleVectorSDNode *Shuf,
// First, check if we are taking one element of a vector and shuffling that
// element into another vector.
ArrayRef<int> Mask = Shuf->getMask();
- SmallVector<int, 16> CommutedMask(Mask.begin(), Mask.end());
+ SmallVector<int, 16> CommutedMask(Mask);
SDValue Op0 = Shuf->getOperand(0);
SDValue Op1 = Shuf->getOperand(1);
int ShufOp0Index = getShuffleMaskIndexOfOneElementFromOp0IntoOp1(Mask);
@@ -22712,7 +22712,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
if (SDValue InsertN1 = ShuffleToInsert(N0, N1, Mask))
return InsertN1;
if (N0.getOpcode() == ISD::CONCAT_VECTORS) {
- SmallVector<int> CommuteMask(Mask.begin(), Mask.end());
+ SmallVector<int> CommuteMask(Mask);
ShuffleVectorSDNode::commuteMask(CommuteMask);
if (SDValue InsertN0 = ShuffleToInsert(N1, N0, CommuteMask))
return InsertN0;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index f17d8eb4be8b7..6752164a5903b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -2286,7 +2286,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
// If Lo or Hi uses elements from at most two of the four input vectors, then
// express it as a vector shuffle of those two inputs. Otherwise extract the
// input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
- SmallVector<int> OrigMask(N->getMask().begin(), N->getMask().end());
+ SmallVector<int> OrigMask(N->getMask());
// Try to pack incoming shuffles/inputs.
auto &&TryPeekThroughShufflesInputs = [&Inputs, &NewVT, this, NewElts,
&DL](SmallVectorImpl<int> &Mask) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 85863324473c2..5ca8d2b3a2849 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1895,7 +1895,7 @@ SDValue SelectionDAG::getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1,
"Index out of range");
// Copy the mask so we can do any needed cleanup.
- SmallVector<int, 8> MaskVec(Mask.begin(), Mask.end());
+ SmallVector<int, 8> MaskVec(Mask);
// Canonicalize shuffle v, v -> v, undef
if (N1 == N2) {
@@ -2051,7 +2051,7 @@ SDValue SelectionDAG::getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1,
SDValue SelectionDAG::getCommutedVectorShuffle(const ShuffleVectorSDNode &SV) {
EVT VT = SV.getValueType(0);
- SmallVector<int, 8> MaskVec(SV.getMask().begin(), SV.getMask().end());
+ SmallVector<int, 8> MaskVec(SV.getMask());
ShuffleVectorSDNode::commuteMask(MaskVec);
SDValue Op0 = SV.getOperand(0);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 40b3f683f56b8..c0ffc73712001 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -3723,7 +3723,7 @@ void SelectionDAGBuilder::visitShuffleVector(const User &I) {
}
// Calculate new mask.
- SmallVector<int, 8> MappedOps(Mask.begin(), Mask.end());
+ SmallVector<int, 8> MappedOps(Mask);
for (int &Idx : MappedOps) {
if (Idx >= (int)SrcNumElts)
Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 0d5066554fce2..8a6595f34c693 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3220,7 +3220,7 @@ bool TargetLowering::SimplifyDemandedVectorElts(
// Simplify mask using undef elements from LHS/RHS.
bool Updated = false;
bool IdentityLHS = true, IdentityRHS = true;
- SmallVector<int, 32> NewMask(ShuffleMask.begin(), ShuffleMask.end());
+ SmallVector<int, 32> NewMask(ShuffleMask);
for (unsigned i = 0; i != NumElts; ++i) {
int &M = NewMask[i];
if (M < 0)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 4c24d70209325..74a985e52ee2c 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -18334,7 +18334,7 @@ SDValue ARMTargetLowering::PerformMVETruncCombine(
if (S0->getOperand(0) == S1->getOperand(0) &&
S0->getOperand(1) == S1->getOperand(1)) {
// Construct complete shuffle mask
- SmallVector<int, 8> Mask(S0->getMask().begin(), S0->getMask().end());
+ SmallVector<int, 8> Mask(S0->getMask());
Mask.append(S1->getMask().begin(), S1->getMask().end());
if (isVMOVNTruncMask(Mask, VT, false))
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
index 0848d30e7403e..4a59610f3d4e2 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
@@ -1149,7 +1149,7 @@ OpRef HvxSelector::packs(ShuffleMask SM, OpRef Va, OpRef Vb,
// Check if we can shuffle vector halves around to get the used elements
// into a single vector.
- SmallVector<int,128> MaskH(SM.Mask.begin(), SM.Mask.end());
+ SmallVector<int, 128> MaskH(SM.Mask);
SmallVector<unsigned, 4> SegList = getInputSegmentList(SM.Mask, SegLen);
unsigned SegCount = SegList.size();
SmallVector<unsigned, 4> SegMap = getOutputSegmentMap(SM.Mask, SegLen);
@@ -1271,11 +1271,11 @@ OpRef HvxSelector::packs(ShuffleMask SM, OpRef Va, OpRef Vb,
ShuffleMask SMH(MaskH);
assert(SMH.Mask.size() == VecLen);
- SmallVector<int,128> MaskA(SMH.Mask.begin(), SMH.Mask.end());
+ SmallVector<int, 128> MaskA(SMH.Mask);
if (SMH.MaxSrc - SMH.MinSrc >= static_cast<int>(HwLen)) {
// valign(Lo=Va,Hi=Vb) won't work. Try swapping Va/Vb.
- SmallVector<int,128> Swapped(SMH.Mask.begin(), SMH.Mask.end());
+ SmallVector<int, 128> Swapped(SMH.Mask);
ShuffleVectorSDNode::commuteMask(Swapped);
ShuffleMask SW(Swapped);
if (SW.MaxSrc - SW.MinSrc < static_cast<int>(HwLen)) {
@@ -1998,7 +1998,7 @@ OpRef HvxSelector::perfect(ShuffleMask SM, OpRef Va, ResultStack &Results) {
// a vector pair, but the two vectors in the pair are swapped.
// The code below that identifies perfect shuffles will reject
// it, unless the order is reversed.
- SmallVector<int,128> MaskStorage(SM.Mask.begin(), SM.Mask.end());
+ SmallVector<int, 128> MaskStorage(SM.Mask);
bool InvertedPair = false;
if (HavePairs && SM.Mask[0] >= int(HwLen)) {
for (int i = 0, e = SM.Mask.size(); i != e; ++i) {
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 8b3a0f9e59124..19e248ec7ef23 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -14885,7 +14885,7 @@ SDValue PPCTargetLowering::combineVectorShuffle(ShuffleVectorSDNode *SVN,
// Adjust the shuffle mask if either input vector comes from a
// SCALAR_TO_VECTOR and keep the respective input vector in permuted
// form (to prevent the need for a swap).
- SmallVector<int, 16> ShuffV(Mask.begin(), Mask.end());
+ SmallVector<int, 16> ShuffV(Mask);
SDValue SToVLHS = isScalarToVec(LHS);
SDValue SToVRHS = isScalarToVec(RHS);
if (SToVLHS || SToVRHS) {
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c52a9642f9dda..78279cbf5e6a4 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -6158,7 +6158,7 @@ static bool canWidenShuffleElements(ArrayRef<int> Mask,
SmallVectorImpl<int> &WidenedMask) {
// Create an alternative mask with info about zeroable elements.
// Here we do not set undef elements as zeroable.
- SmallVector<int, 64> ZeroableMask(Mask.begin(), Mask.end());
+ SmallVector<int, 64> ZeroableMask(Mask);
if (V2IsZero) {
assert(!Zeroable.isZero() && "V2's non-undef elements are used?!");
for (int i = 0, Size = Mask.size(); i != Size; ++i)
@@ -11927,7 +11927,7 @@ static bool is128BitUnpackShuffleMask(ArrayRef<int> Mask,
MVT VT = MVT::getVectorVT(EltVT, Mask.size());
// We can't assume a canonical shuffle mask, so try the commuted version too.
- SmallVector<int, 4> CommutedMask(Mask.begin(), Mask.end());
+ SmallVector<int, 4> CommutedMask(Mask);
ShuffleVectorSDNode::commuteMask(CommutedMask);
// Match any of unary/binary or low/high.
@@ -12786,7 +12786,7 @@ static SDValue lowerShuffleAsBlend(const SDLoc &DL, MVT VT, SDValue V1,
SelectionDAG &DAG) {
uint64_t BlendMask = 0;
bool ForceV1Zero = false, ForceV2Zero = false;
- SmallVector<int, 64> Mask(Original.begin(), Original.end());
+ SmallVector<int, 64> Mask(Original);
if (!matchShuffleAsBlend(V1, V2, Mask, Zeroable, ForceV1Zero, ForceV2Zero,
BlendMask))
return SDValue();
@@ -14242,7 +14242,7 @@ static SDValue lowerShuffleAsElementInsertion(
assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
if (!VT.isFloatingPoint() || V2Index != 0)
return SDValue();
- SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
+ SmallVector<int, 8> V1Mask(Mask);
V1Mask[V2Index] = -1;
if (!isNoopShuffleMask(V1Mask))
return SDValue();
@@ -14391,7 +14391,7 @@ static SDValue lowerShuffleOfExtractsAsVperm(const SDLoc &DL, SDValue N0,
// Match extracts of each half of the wide source vector. Commute the shuffle
// if the extract of the low half is N1.
unsigned NumElts = VT.getVectorNumElements();
- SmallVector<int, 4> NewMask(Mask.begin(), Mask.end());
+ SmallVector<int, 4> NewMask(Mask);
const APInt &ExtIndex0 = N0.getConstantOperandAPInt(1);
const APInt &ExtIndex1 = N1.getConstantOperandAPInt(1);
if (ExtIndex1 == 0 && ExtIndex0 == NumElts)
@@ -14695,7 +14695,7 @@ static bool matchShuffleAsInsertPS(SDValue &V1, SDValue &V2,
return true;
// Commute and try again.
- SmallVector<int, 4> CommutedMask(Mask.begin(), Mask.end());
+ SmallVector<int, 4> CommutedMask(Mask);
ShuffleVectorSDNode::commuteMask(CommutedMask);
if (matchAsInsertPS(V2, V1, CommutedMask))
return true;
@@ -15030,7 +15030,7 @@ static SDValue lowerShuffleWithSHUFPS(const SDLoc &DL, MVT VT,
ArrayRef<int> Mask, SDValue V1,
SDValue V2, SelectionDAG &DAG) {
SDValue LowV = V1, HighV = V2;
- SmallVector<int, 4> NewMask(Mask.begin(), Mask.end());
+ SmallVector<int, 4> NewMask(Mask);
int NumV2Elements = count_if(Mask, [](int M) { return M >= 4; });
if (NumV2Elements == 1) {
@@ -15951,7 +15951,7 @@ static SDValue lowerV8I16Shuffle(const SDLoc &DL, ArrayRef<int> Mask,
return Rotate;
// Make a copy of the mask so it can be modified.
- SmallVector<int, 8> MutableMask(Mask.begin(), Mask.end());
+ SmallVector<int, 8> MutableMask(Mask);
return lowerV8I16GeneralSingleInputShuffle(DL, MVT::v8i16, V1, MutableMask,
Subtarget, DAG);
}
@@ -16135,7 +16135,7 @@ static SDValue lowerShuffleWithPERMV(const SDLoc &DL, MVT VT,
// Adjust mask to correct indices for the second input.
int NumElts = VT.getVectorNumElements();
unsigned Scale = 512 / VT.getSizeInBits();
- SmallVector<int, 32> AdjustedMask(Mask.begin(), Mask.end());
+ SmallVector<int, 32> AdjustedMask(Mask);
for (int &M : AdjustedMask)
if (NumElts <= M)
M += (Scale - 1) * NumElts;
@@ -16881,7 +16881,7 @@ static SDValue lowerShuffleAsLanePermuteAndShuffle(
assert(V2.isUndef() &&
"This last part of this routine only works on single input shuffles");
- SmallVector<int, 32> InLaneMask(Mask.begin(), Mask.end());
+ SmallVector<int, 32> InLaneMask(Mask);
for (int i = 0; i < Size; ++i) {
int &M = InLaneMask[i];
if (M < 0)
@@ -19369,7 +19369,7 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, const X86Subtarget &Subtarget,
// the mask.
if (V2IsUndef &&
any_of(OrigMask, [NumElements](int M) { return M >= NumElements; })) {
- SmallVector<int, 8> NewMask(OrigMask.begin(), OrigMask.end());
+ SmallVector<int, 8> NewMask(OrigMask);
for (int &M : NewMask)
if (M >= NumElements)
M = -1;
@@ -19442,7 +19442,7 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, const X86Subtarget &Subtarget,
}
SmallVector<SDValue> Ops = {V1, V2};
- SmallVector<int> Mask(OrigMask.begin(), OrigMask.end());
+ SmallVector<int> Mask(OrigMask);
// Canonicalize the shuffle with any horizontal ops inputs.
// NOTE: This may update Ops and Mask.
@@ -37692,7 +37692,7 @@ static bool matchBinaryPermuteShuffle(
(MaskVT == MVT::v16i16 && Subtarget.hasAVX2())) {
uint64_t BlendMask = 0;
bool ForceV1Zero = false, ForceV2Zero = false;
- SmallVector<int, 8> TargetMask(Mask.begin(), Mask.end());
+ SmallVector<int, 8> TargetMask(Mask);
if (matchShuffleAsBlend(V1, V2, TargetMask, Zeroable, ForceV1Zero,
ForceV2Zero, BlendMask)) {
if (MaskVT == MVT::v16i16) {
@@ -37895,7 +37895,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
return CanonicalizeShuffleInput(RootVT, V1);
}
- SmallVector<int, 64> Mask(BaseMask.begin(), BaseMask.end());
+ SmallVector<int, 64> Mask(BaseMask);
// See if the shuffle is a hidden identity shuffle - repeated args in HOPs
// etc. can be simplified.
@@ -38638,7 +38638,7 @@ static SDValue combineX86ShuffleChainWithExtract(
for (unsigned i = 1; i != NumInputs; ++i)
Offsets[i] += i * Scale * NumMaskElts;
- SmallVector<int, 64> WideMask(BaseMask.begin(), BaseMask.end());
+ SmallVector<int, 64> WideMask(BaseMask);
for (int &M : WideMask) {
if (M < 0)
continue;
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index e6116642aaa44..d1d5e1f9268b5 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -1865,7 +1865,7 @@ static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx,
SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem";
// One source operand, fix the mask to print all elements in one span.
- SmallVector<int, 8> ShuffleMask(Mask.begin(), Mask.end());
+ SmallVector<int, 8> ShuffleMask(Mask);
if (Src1Name == Src2Name)
for (int i = 0, e = ShuffleMask.size(); i != e; ++i)
if (ShuffleMask[i] >= e)
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 232d1517ce489..0f993403485fb 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -7659,7 +7659,7 @@ class ShuffleInstructionBuilder {
/// Functions adds masks, merging them into single one.
void addMask(ArrayRef<unsigned> SubMask) {
- SmallVector<int, 4> NewMask(SubMask.begin(), SubMask.end());
+ SmallVector<int, 4> NewMask(SubMask);
addMask(NewMask);
}
@@ -8755,7 +8755,7 @@ BoUpSLP::vectorizeTree(ExtraValueToDebugLocsMap &ExternallyUsedValues) {
return PoisonValue::get(FixedVectorType::get(
cast<VectorType>(V1->getType())->getElementType(), Mask.size()));
Value *Op = V1;
- SmallVector<int> CombinedMask(Mask.begin(), Mask.end());
+ SmallVector<int> CombinedMask(Mask);
PeekThroughShuffles(Op, CombinedMask);
if (!isa<FixedVectorType>(Op->getType()) ||
!IsIdentityMask(CombinedMask, cast<FixedVectorType>(Op->getType()))) {
diff --git a/llvm/unittests/ADT/SmallVectorTest.cpp b/llvm/unittests/ADT/SmallVectorTest.cpp
index 1ba3e7e6010c6..db94929f1e9f6 100644
--- a/llvm/unittests/ADT/SmallVectorTest.cpp
+++ b/llvm/unittests/ADT/SmallVectorTest.cpp
@@ -246,6 +246,18 @@ TYPED_TEST(SmallVectorTest, ConstructorIterTest) {
assertValuesInOrder(V, 3u, 1, 2, 3);
}
+// Constructor test.
+TYPED_TEST(SmallVectorTest, ConstructorFromArrayRefSimpleTest) {
+ SCOPED_TRACE("ConstructorFromArrayRefSimpleTest");
+ std::array<Constructable, 3> StdArray = {Constructable(1), Constructable(2),
+ Constructable(3)};
+ ArrayRef<Constructable> Array = StdArray;
+ auto &V = this->theVector;
+ V = SmallVector<Constructable, 4>(Array);
+ assertValuesInOrder(V, 3u, 1, 2, 3);
+ ASSERT_EQ(NumBuiltinElts(TypeParam{}), NumBuiltinElts(V));
+}
+
// New vector test.
TYPED_TEST(SmallVectorTest, EmptyVectorTest) {
SCOPED_TRACE("EmptyVectorTest");
@@ -1130,6 +1142,44 @@ TEST(SmallVectorTest, InitializerList) {
EXPECT_TRUE(makeArrayRef(V2).equals({4, 5, 3, 2}));
}
+struct To {
+ int Content;
+ friend bool operator==(const To &LHS, const To &RHS) {
+ return LHS.Content == RHS.Content;
+ }
+};
+
+class From {
+public:
+ From() = default;
+ From(To M) { T = M; }
+ operator To() const { return T; }
+
+private:
+ To T;
+};
+
+TEST(SmallVectorTest, ConstructFromArrayRefOfConvertibleType) {
+ To to1{1}, to2{2}, to3{3};
+ std::vector<From> StdVector = {From(to1), From(to2), From(to3)};
+ ArrayRef<From> Array = StdVector;
+ {
+ llvm::SmallVector<To> Vector(Array);
+
+ ASSERT_EQ(Array.size(), Vector.size());
+ for (size_t I = 0; I < Array.size(); ++I)
+ EXPECT_EQ(Array[I], Vector[I]);
+ }
+ {
+ llvm::SmallVector<To, 4> Vector(Array);
+
+ ASSERT_EQ(Array.size(), Vector.size());
+ ASSERT_EQ(4u, NumBuiltinElts(Vector));
+ for (size_t I = 0; I < Array.size(); ++I)
+ EXPECT_EQ(Array[I], Vector[I]);
+ }
+}
+
template <class VectorT>
class SmallVectorReferenceInvalidationTest : public SmallVectorTestBase {
protected:
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