[PATCH] D131165: [AArch64] Fix and add A64FX scheduling resource/latency info

[Yuta Mukai via Phabricator via llvm-commits]

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1. Missing instruction information (FTSSEL, FMSB, PFIRST and RDFFR) is added and CompleteModel is set to one.

2. Information for pseudo SVE instructions is added. Those instructions are present at the time of scheduling.

3. Resource and latency information for SVE instructions is modified to be more accurate. For example, the description for CMPEQ, which consumes one cycle each of unit FLA and PPR, is as follows.

  Previous:
    def A64FXGI01 : ProcResGroup<[A64FXIPFLA, A64FXIPPR]>;
    def A64FXWrite_4Cyc_GI01 : SchedWriteRes<[A64FXGI01]> {...
  Modified:
    def A64FXGI0 : ProcResGroup<[A64FXIPFLA]>;
    def A64FXGI1 : ProcResGroup<[A64FXIPPR]>;
    def A64FXWrite_CMP : SchedWriteRes<[A64FXGI0, A64FXGI1]> {...

Reference: A64FX Microarchitecture Manual (Table 16-3)
https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_Microarchitecture_Manual_en_1.7.pdf

Although this patch will significantly change the resource/latency information for SVE instructions, I believe that the change in scheduling results will be small. This is because minimizing register pressure is a priority in scheduling for this machine. (According to GenericScheduler::tryCandidate() at MachineScheduler.cpp)

I would like to implement more aggressive scheduling (such as pipelining) and this modification is necessary for that.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D131165

Files:
  llvm/lib/Target/AArch64/AArch64SchedA64FX.td
  llvm/test/tools/llvm-mca/AArch64/A64FX/A64-basic-instructions.s
  llvm/test/tools/llvm-mca/AArch64/A64FX/A64FX-neon-instructions.s
  llvm/test/tools/llvm-mca/AArch64/A64FX/A64FX-sve-instructions.s