[llvm] 45bae1b - [RISCV][test] Add inloop reduction vectorize test. NFC
via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 4 00:07:08 PDT 2022
Author: jacquesguan
Date: 2022-08-04T15:06:44+08:00
New Revision: 45bae1be90472c696f6ba3bb4f8fabee76040fa9
URL: https://github.com/llvm/llvm-project/commit/45bae1be90472c696f6ba3bb4f8fabee76040fa9
DIFF: https://github.com/llvm/llvm-project/commit/45bae1be90472c696f6ba3bb4f8fabee76040fa9.diff
LOG: [RISCV][test] Add inloop reduction vectorize test. NFC
Added:
llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll b/llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
new file mode 100644
index 0000000000000..ecac838b23c01
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
@@ -0,0 +1,169 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -mtriple riscv64-linux-gnu -mattr=+v,+d -loop-vectorize < %s -S -o - | FileCheck %s -check-prefix=OUTLOOP
+; RUN: opt -mtriple riscv64-linux-gnu -mattr=+v,+d -loop-vectorize -prefer-inloop-reductions < %s -S -o - | FileCheck %s -check-prefix=INLOOP
+
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+target triple = "riscv64"
+
+define i32 @add_i16_i32(i16* nocapture readonly %x, i32 %n) {
+; OUTLOOP-LABEL: @add_i16_i32(
+; OUTLOOP-NEXT: entry:
+; OUTLOOP-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0
+; OUTLOOP-NEXT: br i1 [[CMP6]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]]
+; OUTLOOP: for.body.preheader:
+; OUTLOOP-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32()
+; OUTLOOP-NEXT: [[TMP1:%.*]] = mul i32 [[TMP0]], 4
+; OUTLOOP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], [[TMP1]]
+; OUTLOOP-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; OUTLOOP: vector.ph:
+; OUTLOOP-NEXT: [[TMP2:%.*]] = call i32 @llvm.vscale.i32()
+; OUTLOOP-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], 4
+; OUTLOOP-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], [[TMP3]]
+; OUTLOOP-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
+; OUTLOOP-NEXT: br label [[VECTOR_BODY:%.*]]
+; OUTLOOP: vector.body:
+; OUTLOOP-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; OUTLOOP-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP20:%.*]], [[VECTOR_BODY]] ]
+; OUTLOOP-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP21:%.*]], [[VECTOR_BODY]] ]
+; OUTLOOP-NEXT: [[TMP4:%.*]] = add i32 [[INDEX]], 0
+; OUTLOOP-NEXT: [[TMP5:%.*]] = call i32 @llvm.vscale.i32()
+; OUTLOOP-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], 2
+; OUTLOOP-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], 0
+; OUTLOOP-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], 1
+; OUTLOOP-NEXT: [[TMP9:%.*]] = add i32 [[INDEX]], [[TMP8]]
+; OUTLOOP-NEXT: [[TMP10:%.*]] = getelementptr inbounds i16, i16* [[X:%.*]], i32 [[TMP4]]
+; OUTLOOP-NEXT: [[TMP11:%.*]] = getelementptr inbounds i16, i16* [[X]], i32 [[TMP9]]
+; OUTLOOP-NEXT: [[TMP12:%.*]] = getelementptr inbounds i16, i16* [[TMP10]], i32 0
+; OUTLOOP-NEXT: [[TMP13:%.*]] = bitcast i16* [[TMP12]] to <vscale x 2 x i16>*
+; OUTLOOP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x i16>, <vscale x 2 x i16>* [[TMP13]], align 2
+; OUTLOOP-NEXT: [[TMP14:%.*]] = call i32 @llvm.vscale.i32()
+; OUTLOOP-NEXT: [[TMP15:%.*]] = mul i32 [[TMP14]], 2
+; OUTLOOP-NEXT: [[TMP16:%.*]] = getelementptr inbounds i16, i16* [[TMP10]], i32 [[TMP15]]
+; OUTLOOP-NEXT: [[TMP17:%.*]] = bitcast i16* [[TMP16]] to <vscale x 2 x i16>*
+; OUTLOOP-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 2 x i16>, <vscale x 2 x i16>* [[TMP17]], align 2
+; OUTLOOP-NEXT: [[TMP18:%.*]] = sext <vscale x 2 x i16> [[WIDE_LOAD]] to <vscale x 2 x i32>
+; OUTLOOP-NEXT: [[TMP19:%.*]] = sext <vscale x 2 x i16> [[WIDE_LOAD2]] to <vscale x 2 x i32>
+; OUTLOOP-NEXT: [[TMP20]] = add <vscale x 2 x i32> [[VEC_PHI]], [[TMP18]]
+; OUTLOOP-NEXT: [[TMP21]] = add <vscale x 2 x i32> [[VEC_PHI1]], [[TMP19]]
+; OUTLOOP-NEXT: [[TMP22:%.*]] = call i32 @llvm.vscale.i32()
+; OUTLOOP-NEXT: [[TMP23:%.*]] = mul i32 [[TMP22]], 4
+; OUTLOOP-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], [[TMP23]]
+; OUTLOOP-NEXT: [[TMP24:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; OUTLOOP-NEXT: br i1 [[TMP24]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; OUTLOOP: middle.block:
+; OUTLOOP-NEXT: [[BIN_RDX:%.*]] = add <vscale x 2 x i32> [[TMP21]], [[TMP20]]
+; OUTLOOP-NEXT: [[TMP25:%.*]] = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> [[BIN_RDX]])
+; OUTLOOP-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
+; OUTLOOP-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]], label [[SCALAR_PH]]
+; OUTLOOP: scalar.ph:
+; OUTLOOP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER]] ]
+; OUTLOOP-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[TMP25]], [[MIDDLE_BLOCK]] ]
+; OUTLOOP-NEXT: br label [[FOR_BODY:%.*]]
+; OUTLOOP: for.body:
+; OUTLOOP-NEXT: [[I_08:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
+; OUTLOOP-NEXT: [[R_07:%.*]] = phi i32 [ [[ADD:%.*]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
+; OUTLOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[X]], i32 [[I_08]]
+; OUTLOOP-NEXT: [[TMP26:%.*]] = load i16, i16* [[ARRAYIDX]], align 2
+; OUTLOOP-NEXT: [[CONV:%.*]] = sext i16 [[TMP26]] to i32
+; OUTLOOP-NEXT: [[ADD]] = add nsw i32 [[R_07]], [[CONV]]
+; OUTLOOP-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 1
+; OUTLOOP-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
+; OUTLOOP-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]]
+; OUTLOOP: for.cond.cleanup.loopexit:
+; OUTLOOP-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_BODY]] ], [ [[TMP25]], [[MIDDLE_BLOCK]] ]
+; OUTLOOP-NEXT: br label [[FOR_COND_CLEANUP]]
+; OUTLOOP: for.cond.cleanup:
+; OUTLOOP-NEXT: [[R_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD_LCSSA]], [[FOR_COND_CLEANUP_LOOPEXIT]] ]
+; OUTLOOP-NEXT: ret i32 [[R_0_LCSSA]]
+;
+; INLOOP-LABEL: @add_i16_i32(
+; INLOOP-NEXT: entry:
+; INLOOP-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0
+; INLOOP-NEXT: br i1 [[CMP6]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]]
+; INLOOP: for.body.preheader:
+; INLOOP-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32()
+; INLOOP-NEXT: [[TMP1:%.*]] = mul i32 [[TMP0]], 8
+; INLOOP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], [[TMP1]]
+; INLOOP-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; INLOOP: vector.ph:
+; INLOOP-NEXT: [[TMP2:%.*]] = call i32 @llvm.vscale.i32()
+; INLOOP-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], 8
+; INLOOP-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], [[TMP3]]
+; INLOOP-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
+; INLOOP-NEXT: br label [[VECTOR_BODY:%.*]]
+; INLOOP: vector.body:
+; INLOOP-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; INLOOP-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP21:%.*]], [[VECTOR_BODY]] ]
+; INLOOP-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP23:%.*]], [[VECTOR_BODY]] ]
+; INLOOP-NEXT: [[TMP4:%.*]] = add i32 [[INDEX]], 0
+; INLOOP-NEXT: [[TMP5:%.*]] = call i32 @llvm.vscale.i32()
+; INLOOP-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], 4
+; INLOOP-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], 0
+; INLOOP-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], 1
+; INLOOP-NEXT: [[TMP9:%.*]] = add i32 [[INDEX]], [[TMP8]]
+; INLOOP-NEXT: [[TMP10:%.*]] = getelementptr inbounds i16, i16* [[X:%.*]], i32 [[TMP4]]
+; INLOOP-NEXT: [[TMP11:%.*]] = getelementptr inbounds i16, i16* [[X]], i32 [[TMP9]]
+; INLOOP-NEXT: [[TMP12:%.*]] = getelementptr inbounds i16, i16* [[TMP10]], i32 0
+; INLOOP-NEXT: [[TMP13:%.*]] = bitcast i16* [[TMP12]] to <vscale x 4 x i16>*
+; INLOOP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i16>, <vscale x 4 x i16>* [[TMP13]], align 2
+; INLOOP-NEXT: [[TMP14:%.*]] = call i32 @llvm.vscale.i32()
+; INLOOP-NEXT: [[TMP15:%.*]] = mul i32 [[TMP14]], 4
+; INLOOP-NEXT: [[TMP16:%.*]] = getelementptr inbounds i16, i16* [[TMP10]], i32 [[TMP15]]
+; INLOOP-NEXT: [[TMP17:%.*]] = bitcast i16* [[TMP16]] to <vscale x 4 x i16>*
+; INLOOP-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 4 x i16>, <vscale x 4 x i16>* [[TMP17]], align 2
+; INLOOP-NEXT: [[TMP18:%.*]] = sext <vscale x 4 x i16> [[WIDE_LOAD]] to <vscale x 4 x i32>
+; INLOOP-NEXT: [[TMP19:%.*]] = sext <vscale x 4 x i16> [[WIDE_LOAD2]] to <vscale x 4 x i32>
+; INLOOP-NEXT: [[TMP20:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> [[TMP18]])
+; INLOOP-NEXT: [[TMP21]] = add i32 [[TMP20]], [[VEC_PHI]]
+; INLOOP-NEXT: [[TMP22:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> [[TMP19]])
+; INLOOP-NEXT: [[TMP23]] = add i32 [[TMP22]], [[VEC_PHI1]]
+; INLOOP-NEXT: [[TMP24:%.*]] = call i32 @llvm.vscale.i32()
+; INLOOP-NEXT: [[TMP25:%.*]] = mul i32 [[TMP24]], 8
+; INLOOP-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], [[TMP25]]
+; INLOOP-NEXT: [[TMP26:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; INLOOP-NEXT: br i1 [[TMP26]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; INLOOP: middle.block:
+; INLOOP-NEXT: [[BIN_RDX:%.*]] = add i32 [[TMP23]], [[TMP21]]
+; INLOOP-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
+; INLOOP-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]], label [[SCALAR_PH]]
+; INLOOP: scalar.ph:
+; INLOOP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER]] ]
+; INLOOP-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[BIN_RDX]], [[MIDDLE_BLOCK]] ]
+; INLOOP-NEXT: br label [[FOR_BODY:%.*]]
+; INLOOP: for.body:
+; INLOOP-NEXT: [[I_08:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
+; INLOOP-NEXT: [[R_07:%.*]] = phi i32 [ [[ADD:%.*]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
+; INLOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[X]], i32 [[I_08]]
+; INLOOP-NEXT: [[TMP27:%.*]] = load i16, i16* [[ARRAYIDX]], align 2
+; INLOOP-NEXT: [[CONV:%.*]] = sext i16 [[TMP27]] to i32
+; INLOOP-NEXT: [[ADD]] = add nsw i32 [[R_07]], [[CONV]]
+; INLOOP-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 1
+; INLOOP-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
+; INLOOP-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]]
+; INLOOP: for.cond.cleanup.loopexit:
+; INLOOP-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_BODY]] ], [ [[BIN_RDX]], [[MIDDLE_BLOCK]] ]
+; INLOOP-NEXT: br label [[FOR_COND_CLEANUP]]
+; INLOOP: for.cond.cleanup:
+; INLOOP-NEXT: [[R_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD_LCSSA]], [[FOR_COND_CLEANUP_LOOPEXIT]] ]
+; INLOOP-NEXT: ret i32 [[R_0_LCSSA]]
+;
+entry:
+ %cmp6 = icmp sgt i32 %n, 0
+ br i1 %cmp6, label %for.body, label %for.cond.cleanup
+
+for.body: ; preds = %entry, %for.body
+ %i.08 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
+ %r.07 = phi i32 [ %add, %for.body ], [ 0, %entry ]
+ %arrayidx = getelementptr inbounds i16, i16* %x, i32 %i.08
+ %0 = load i16, i16* %arrayidx, align 2
+ %conv = sext i16 %0 to i32
+ %add = add nsw i32 %r.07, %conv
+ %inc = add nuw nsw i32 %i.08, 1
+ %exitcond = icmp eq i32 %inc, %n
+ br i1 %exitcond, label %for.cond.cleanup, label %for.body
+
+for.cond.cleanup: ; preds = %for.body, %entry
+ %r.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
+ ret i32 %r.0.lcssa
+}
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