[PATCH] D128642: [AArch64][SVE] Use SVE for VLS fcopysign for wide vectors

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added a comment.

Documentation for combiner-vector-fcopysign-extend-round needs updating but otherwise looks good.



================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:141
+    cl::desc("Enable merging extends and rounds into FCOPYSIGN on vector types "
+             "to test additional FCOPYSIGN lowering paths"));
+
----------------
Please drop this part of the documentation.  Although this is why you've added the flag, it is not the only reason somebody might want to use it (i.e. somebody might actually want to enable the optimisation).


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:3615-3618
+  SDValue Concat =
+      DAG.getNode(ISD::CONCAT_VECTORS, DL, N->getValueType(0), Lo, Hi);
+
+  return Concat;
----------------
You could just `return DAG.getNode(...`.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7776
   SDValue In2 = Op.getOperand(1);
+
   EVT SrcVT = In2.getValueType();
----------------
Bogus blank line.


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https://reviews.llvm.org/D128642