[PATCH] D130618: [AArch64][LoopVectorize] Enable tail-folding by default for SVE

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Aug 3 04:36:44 PDT 2022


dmgreen added a comment.

Can you explain more about why reductions are a problem for certain cpus? What about the cortex-a510? And if it being disabled for all these cpus, should it be disabled for -mcpu=generic too?  I'm not sure why we would disable sve reductions though - first-order-recurrences make more sense, but that might be something that is better is done in general, not per-subtarget.

And is tail-folding expected to be beneficial in general? As far as I can see it might currently be losing the interleaving, which can be important for performance. And it should ideally not be altering the NEON codegen, if that could be preferable. Is this currently one option that alters both scalable and fixed width vectorization?



================
Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:122
+void setSVETailFoldingDefaultOpts(uint8_t V) {
+  TailFoldingOptionLoc.setDefault(V);
+}
----------------
Is this setting a global variable? I think it should be just a field in the subtarget (maybe a subtarget feature), that is potentially overridden by the option if it is present.


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  https://reviews.llvm.org/D130618/new/

https://reviews.llvm.org/D130618



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