[PATCH] D130100: [AArch64] Combine a load into GPR followed by a copy to FPR to a load into FPR directly through MIPeepholeOpt

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

I worry about the potential for bugs in any patch in the AArch64MIPeepholeOptimizer. And loading makes that more complex. The altered tests look like they are either intrinsics like the pmull64 that was recently changed or strange types (<32 x i1>, <16 x i12>) that don't come up a lot in practice. The global-isel change in dp1.ll is a missed fold that is probably better handled in global-isel. The irregular type tests also show it only handling straight loads, not instructions like `ld1 { v1.s }[1], [x12]`. The current model is to try and handle almost all combines during ISel so that they can all work together in one place.

If this comes up in more places it might be worth it. From the examples in the tests I'm not so sure though. Do you have any other examples where this helps?


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  https://reviews.llvm.org/D130100/new/

https://reviews.llvm.org/D130100