[llvm] 646e2f4 - [VP] Rename VP int<->float conversion ISD opcodes
Fraser Cormack via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 3 02:16:41 PDT 2022
Author: Fraser Cormack
Date: 2022-08-03T10:04:38+01:00
New Revision: 646e2f48033626cb6ca6d45825b0cbe98ec29ec1
URL: https://github.com/llvm/llvm-project/commit/646e2f48033626cb6ca6d45825b0cbe98ec29ec1
DIFF: https://github.com/llvm/llvm-project/commit/646e2f48033626cb6ca6d45825b0cbe98ec29ec1.diff
LOG: [VP] Rename VP int<->float conversion ISD opcodes
These should be named like the non-VP versions for consistency.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D130967
Added:
Modified:
llvm/include/llvm/IR/VPIntrinsics.def
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/IR/VPIntrinsics.def b/llvm/include/llvm/IR/VPIntrinsics.def
index 1d639e8aeb016..17ec516172789 100644
--- a/llvm/include/llvm/IR/VPIntrinsics.def
+++ b/llvm/include/llvm/IR/VPIntrinsics.def
@@ -257,16 +257,16 @@ END_REGISTER_VP(vp_fma, VP_FMA)
END_REGISTER_VP(vp_##OPSUFFIX, VPSD)
// llvm.vp.fptoui(x,mask,vlen)
-HELPER_REGISTER_FP_CAST_VP(fptoui, VP_FPTOUI, FPToUI, 0)
+HELPER_REGISTER_FP_CAST_VP(fptoui, VP_FP_TO_UINT, FPToUI, 0)
// llvm.vp.fptosi(x,mask,vlen)
-HELPER_REGISTER_FP_CAST_VP(fptosi, VP_FPTOSI, FPToSI, 0)
+HELPER_REGISTER_FP_CAST_VP(fptosi, VP_FP_TO_SINT, FPToSI, 0)
// llvm.vp.uitofp(x,mask,vlen)
-HELPER_REGISTER_FP_CAST_VP(uitofp, VP_UITOFP, UIToFP, 1)
+HELPER_REGISTER_FP_CAST_VP(uitofp, VP_UINT_TO_FP, UIToFP, 1)
// llvm.vp.sitofp(x,mask,vlen)
-HELPER_REGISTER_FP_CAST_VP(sitofp, VP_SITOFP, SIToFP, 1)
+HELPER_REGISTER_FP_CAST_VP(sitofp, VP_SINT_TO_FP, SIToFP, 1)
// llvm.vp.fptrunc(x,mask,vlen)
HELPER_REGISTER_FP_CAST_VP(fptrunc, VP_FP_ROUND, FPTrunc, 1)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 228d4a43ccde1..ff26d0fe77264 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -137,8 +137,8 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::ZERO_EXTEND:
case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
- case ISD::VP_FPTOSI:
- case ISD::VP_FPTOUI:
+ case ISD::VP_FP_TO_SINT:
+ case ISD::VP_FP_TO_UINT:
case ISD::STRICT_FP_TO_SINT:
case ISD::STRICT_FP_TO_UINT:
case ISD::FP_TO_SINT:
@@ -673,10 +673,10 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
TLI.isOperationLegalOrCustom(ISD::STRICT_FP_TO_SINT, NVT))
NewOpc = ISD::STRICT_FP_TO_SINT;
- if (N->getOpcode() == ISD::VP_FPTOUI &&
- !TLI.isOperationLegal(ISD::VP_FPTOUI, NVT) &&
- TLI.isOperationLegalOrCustom(ISD::VP_FPTOSI, NVT))
- NewOpc = ISD::VP_FPTOSI;
+ if (N->getOpcode() == ISD::VP_FP_TO_UINT &&
+ !TLI.isOperationLegal(ISD::VP_FP_TO_UINT, NVT) &&
+ TLI.isOperationLegalOrCustom(ISD::VP_FP_TO_SINT, NVT))
+ NewOpc = ISD::VP_FP_TO_SINT;
SDValue Res;
if (N->isStrictFPOpcode()) {
@@ -685,7 +685,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
// Legalize the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
- } else if (NewOpc == ISD::VP_FPTOSI || NewOpc == ISD::VP_FPTOUI) {
+ } else if (NewOpc == ISD::VP_FP_TO_SINT || NewOpc == ISD::VP_FP_TO_UINT) {
Res = DAG.getNode(NewOpc, dl, NVT, {N->getOperand(0), N->getOperand(1),
N->getOperand(2)});
} else {
@@ -701,7 +701,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
// after legalization: fp-to-sint32, 65534. -> 0x0000fffe
return DAG.getNode((N->getOpcode() == ISD::FP_TO_UINT ||
N->getOpcode() == ISD::STRICT_FP_TO_UINT ||
- N->getOpcode() == ISD::VP_FPTOUI)
+ N->getOpcode() == ISD::VP_FP_TO_UINT)
? ISD::AssertZext
: ISD::AssertSext,
dl, NVT, Res,
@@ -1648,7 +1648,7 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
case ISD::VP_SETCC:
case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
- case ISD::VP_SITOFP:
+ case ISD::VP_SINT_TO_FP:
case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
case ISD::STRICT_SINT_TO_FP: Res = PromoteIntOp_STRICT_SINT_TO_FP(N); break;
case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
@@ -1664,7 +1664,7 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
case ISD::VP_TRUNCATE:
case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
case ISD::FP16_TO_FP:
- case ISD::VP_UITOFP:
+ case ISD::VP_UINT_TO_FP:
case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
case ISD::STRICT_UINT_TO_FP: Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
@@ -1998,7 +1998,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
}
SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
- if (N->getOpcode() == ISD::VP_SITOFP)
+ if (N->getOpcode() == ISD::VP_SINT_TO_FP)
return SDValue(DAG.UpdateNodeOperands(N,
SExtPromotedInteger(N->getOperand(0)),
N->getOperand(1), N->getOperand(2)),
@@ -2127,7 +2127,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
}
SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
- if (N->getOpcode() == ISD::VP_UITOFP)
+ if (N->getOpcode() == ISD::VP_UINT_TO_FP)
return SDValue(DAG.UpdateNodeOperands(N,
ZExtPromotedInteger(N->getOperand(0)),
N->getOperand(1), N->getOperand(2)),
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 143abc08eeeab..7cafa7d3a56d8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -1031,9 +1031,9 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::FP_ROUND:
case ISD::VP_FP_ROUND:
case ISD::FP_TO_SINT:
- case ISD::VP_FPTOSI:
+ case ISD::VP_FP_TO_SINT:
case ISD::FP_TO_UINT:
- case ISD::VP_FPTOUI:
+ case ISD::VP_FP_TO_UINT:
case ISD::FRINT:
case ISD::FROUND:
case ISD::FROUNDEVEN:
@@ -1041,11 +1041,11 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::FSQRT:
case ISD::FTRUNC:
case ISD::SINT_TO_FP:
- case ISD::VP_SITOFP:
+ case ISD::VP_SINT_TO_FP:
case ISD::TRUNCATE:
case ISD::VP_TRUNCATE:
case ISD::UINT_TO_FP:
- case ISD::VP_UITOFP:
+ case ISD::VP_UINT_TO_FP:
case ISD::FCANONICALIZE:
SplitVecRes_UnaryOp(N, Lo, Hi);
break;
@@ -3809,17 +3809,17 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
case ISD::FP_ROUND:
case ISD::VP_FP_ROUND:
case ISD::FP_TO_SINT:
- case ISD::VP_FPTOSI:
+ case ISD::VP_FP_TO_SINT:
case ISD::FP_TO_UINT:
- case ISD::VP_FPTOUI:
+ case ISD::VP_FP_TO_UINT:
case ISD::SIGN_EXTEND:
case ISD::VP_SIGN_EXTEND:
case ISD::SINT_TO_FP:
- case ISD::VP_SITOFP:
+ case ISD::VP_SINT_TO_FP:
case ISD::VP_TRUNCATE:
case ISD::TRUNCATE:
case ISD::UINT_TO_FP:
- case ISD::VP_UITOFP:
+ case ISD::VP_UINT_TO_FP:
case ISD::ZERO_EXTEND:
case ISD::VP_ZERO_EXTEND:
Res = WidenVecRes_Convert(N);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d89f6b9c6c908..af5dae9f3284d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -443,8 +443,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VP_SHL, ISD::VP_REDUCE_ADD, ISD::VP_REDUCE_AND,
ISD::VP_REDUCE_OR, ISD::VP_REDUCE_XOR, ISD::VP_REDUCE_SMAX,
ISD::VP_REDUCE_SMIN, ISD::VP_REDUCE_UMAX, ISD::VP_REDUCE_UMIN,
- ISD::VP_MERGE, ISD::VP_SELECT, ISD::VP_FPTOSI,
- ISD::VP_FPTOUI, ISD::VP_SETCC, ISD::VP_SIGN_EXTEND,
+ ISD::VP_MERGE, ISD::VP_SELECT, ISD::VP_FP_TO_SINT,
+ ISD::VP_FP_TO_UINT, ISD::VP_SETCC, ISD::VP_SIGN_EXTEND,
ISD::VP_ZERO_EXTEND, ISD::VP_TRUNCATE};
static const unsigned FloatingPointVPOps[] = {
@@ -454,7 +454,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VP_REDUCE_FADD, ISD::VP_REDUCE_SEQ_FADD,
ISD::VP_REDUCE_FMIN, ISD::VP_REDUCE_FMAX,
ISD::VP_MERGE, ISD::VP_SELECT,
- ISD::VP_SITOFP, ISD::VP_UITOFP,
+ ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP,
ISD::VP_SETCC, ISD::VP_FP_ROUND,
ISD::VP_FP_EXTEND};
@@ -527,9 +527,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
VT, Expand);
}
- setOperationAction(
- {ISD::VP_FPTOSI, ISD::VP_FPTOUI, ISD::VP_TRUNCATE, ISD::VP_SETCC}, VT,
- Custom);
+ setOperationAction({ISD::VP_FP_TO_SINT, ISD::VP_FP_TO_UINT,
+ ISD::VP_TRUNCATE, ISD::VP_SETCC},
+ VT, Custom);
setOperationAction(ISD::VECTOR_REVERSE, VT, Custom);
setOperationPromotedToType(
@@ -792,9 +792,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::OR, ISD::XOR},
VT, Custom);
- setOperationAction(
- {ISD::VP_FPTOSI, ISD::VP_FPTOUI, ISD::VP_SETCC, ISD::VP_TRUNCATE},
- VT, Custom);
+ setOperationAction({ISD::VP_FP_TO_SINT, ISD::VP_FP_TO_UINT,
+ ISD::VP_SETCC, ISD::VP_TRUNCATE},
+ VT, Custom);
continue;
}
@@ -3730,13 +3730,13 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::VP_FP_EXTEND:
case ISD::VP_FP_ROUND:
return lowerVectorFPExtendOrRoundLike(Op, DAG);
- case ISD::VP_FPTOSI:
+ case ISD::VP_FP_TO_SINT:
return lowerVPFPIntConvOp(Op, DAG, RISCVISD::FP_TO_SINT_VL);
- case ISD::VP_FPTOUI:
+ case ISD::VP_FP_TO_UINT:
return lowerVPFPIntConvOp(Op, DAG, RISCVISD::FP_TO_UINT_VL);
- case ISD::VP_SITOFP:
+ case ISD::VP_SINT_TO_FP:
return lowerVPFPIntConvOp(Op, DAG, RISCVISD::SINT_TO_FP_VL);
- case ISD::VP_UITOFP:
+ case ISD::VP_UINT_TO_FP:
return lowerVPFPIntConvOp(Op, DAG, RISCVISD::UINT_TO_FP_VL);
case ISD::VP_SETCC:
if (Op.getOperand(0).getSimpleValueType().getVectorElementType() == MVT::i1)
More information about the llvm-commits
mailing list