[PATCH] D131018: [AArch64] A tablegen pattern to handle pmull2

[Mingming Liu via Phabricator via llvm-commits]

mingmingl added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll:33
 ; CHECK-NEXT:    fmov d1, x9
-; CHECK-NEXT:    pmull v0.1q, v0.1d, v1.1d
+; CHECK-NEXT:    dup v1.2d, v1.d[0]
+; CHECK-NEXT:    pmull2 v0.1q, v0.2d, v1.2d
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mingmingl wrote:
> efriedma wrote:
> > Are you intentionally avoiding the variant of "dup" that takes a GPR operand (DUPv2i64gpr)?
> Nope, no intention to hack this.
> 
> It's good that the FPR/SIMD version of DUP is generated, since it takes 2 cycles; while the GPR version takes 3 cycles (so more expensive than the MOV from FPR to GPR).
> 
> I think it's handled by some combining / peephole, but need to verify it.
Added `test5` in `llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll` to show that this is a win when one source operand is from GPR (`%2` in `define void @test5(ptr %0, <2 x i64> %1, i64 %2) {`). 


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https://reviews.llvm.org/D131018