[PATCH] D131018: [AArch64] A tablegen pattern to handle pmull2
Mingming Liu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 2 14:20:12 PDT 2022
mingmingl marked an inline comment as done.
mingmingl added inline comments.
================
Comment at: llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll:33
; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: pmull v0.1q, v0.1d, v1.1d
+; CHECK-NEXT: dup v1.2d, v1.d[0]
+; CHECK-NEXT: pmull2 v0.1q, v0.2d, v1.2d
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efriedma wrote:
> Are you intentionally avoiding the variant of "dup" that takes a GPR operand (DUPv2i64gpr)?
Nope, no intention to hack this.
It's good that the FPR/SIMD version of DUP is generated, since it takes 2 cycles; while the GPR version takes 3 cycles (so more expensive than the MOV from FPR to GPR).
I think it's handled by some combining / peephole, but need to verify it.
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https://reviews.llvm.org/D131018/new/
https://reviews.llvm.org/D131018
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