[PATCH] D130191: [RISCV] Teach ComputeNumSignBitsForTargetNode about masked atomic intrinsics

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D130191#3694550 <https://reviews.llvm.org/D130191#3694550>, @reames wrote:

> LGTM w/requested changes.
>
> As an optional follow up, I find myself wondering if the 64 bit versions should actually have a 64 bit return type.  Having them instead have i32 operands and return types - to model the emulated access actually being done - and then explicitly sign extended afterwards would get the same effect here with less code and less confusion.

Wouldn't that require the intrinsics to go through type legalization to be promoted to a new RISCVISD node with i64 types? And then we'd need to teach computeKnownSignBits about the new RISCVISD node so we could remove in sext_inreg that got created from the sign_extend.

Unless I'm misunderstanding what you're proposing?


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