[llvm] 2e5c516 - [RISCV] Add scheduler class to PseudoReadVLENB.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-08-02T09:38:32-07:00
New Revision: 2e5c516a3d6953edbc66072a82f88371ff668e9d

URL: https://github.com/llvm/llvm-project/commit/2e5c516a3d6953edbc66072a82f88371ff668e9d
DIFF: https://github.com/llvm/llvm-project/commit/2e5c516a3d6953edbc66072a82f88371ff668e9d.diff

LOG: [RISCV] Add scheduler class to PseudoReadVLENB.

Reviewed By: monkchiang

Differential Revision: https://reviews.llvm.org/D130938

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    llvm/lib/Target/RISCV/RISCVScheduleV.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index fbe396d278b4b..8bae021fe1246 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -4332,7 +4332,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1 in {
   def PseudoReadVLENB : Pseudo<(outs GPR:$rd), (ins),
-                               [(set GPR:$rd, (riscv_read_vlenb))]>;
+                               [(set GPR:$rd, (riscv_read_vlenb))]>,
+                        Sched<[WriteRdVLENB]>;
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1,

diff  --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index bafcf47b82e43..6b648cb31f405 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -9,6 +9,9 @@
 //===----------------------------------------------------------------------===//
 /// Define scheduler resources associated with def operands.
 
+// 3.6 Vector Byte Length vlenb
+def WriteRdVLENB      : SchedWrite;
+
 // 7. Vector Loads and Stores
 // 7.4. Vector Unit-Stride Instructions
 def WriteVLDE8        : SchedWrite;
@@ -493,6 +496,9 @@ def ReadVMask         : SchedRead;
 multiclass UnsupportedSchedV {
 let Unsupported = true in {
 
+// 3.6 Vector Byte Length vlenb
+def : WriteRes<WriteRdVLENB, []>;
+
 // 7. Vector Loads and Stores
 def : WriteRes<WriteVLDE8, []>;
 def : WriteRes<WriteVLDE16, []>;