[PATCH] D130367: [AMDGPU] avoid blind converting to VALU REG_SEQUENCE and PHIs

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp:923
+      Register Reg = Inst->getOperand(0).getReg();
+      if (TRI->isSGPRReg(*MRI, Reg) && !(TII->isVALU(*Inst)))
+        for (auto &U : MRI->use_instructions(Reg))
----------------
Don't need parens around TII->isVALU


================
Comment at: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp:1004
 
-      // Compute the COPY width to pass it to V2SCopyInfo Ctor
-      Register DstReg = MI.getOperand(0).getReg();
+      if ((MI->isRegSequence() || MI->isPHI())) {
+        MachineBasicBlock::iterator J = I;
----------------
Don't need the outer parens.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130367/new/

https://reviews.llvm.org/D130367