[PATCH] D129994: [RISCV] Add cost modelling for vector widenning integer reduction.
Jianjian Guan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 2 03:34:12 PDT 2022
jacquesguan updated this revision to Diff 449248.
jacquesguan added a comment.
Refactor the code.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D129994/new/
https://reviews.llvm.org/D129994
Files:
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
Index: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -112,6 +112,11 @@
Optional<FastMathFlags> FMF,
TTI::TargetCostKind CostKind);
+ InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned,
+ Type *ResTy, VectorType *ValTy,
+ Optional<FastMathFlags> FMF,
+ TTI::TargetCostKind CostKind);
+
bool isElementTypeLegalForScalableVector(Type *Ty) const {
return TLI->isLegalElementTypeForRVV(Ty);
}
Index: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -377,6 +377,43 @@
return (LT.first - 1) + BaseCost + Log2_32_Ceil(VL);
}
+InstructionCost RISCVTTIImpl::getExtendedReductionCost(
+ unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *ValTy,
+ Optional<FastMathFlags> FMF, TTI::TargetCostKind CostKind) {
+ if (isa<FixedVectorType>(ValTy) && !ST->useRVVForFixedLengthVectors())
+ return BaseT::getExtendedReductionCost(Opcode, IsUnsigned, ResTy, ValTy,
+ FMF, CostKind);
+
+ // Skip if scalar size of ResTy is bigger than ELEN.
+ if (ResTy->getScalarSizeInBits() > ST->getELEN())
+ return BaseT::getExtendedReductionCost(Opcode, IsUnsigned, ResTy, ValTy,
+ FMF, CostKind);
+
+ int ISD = TLI->InstructionOpcodeToISD(Opcode);
+ assert(ISD && "Invalid opcode");
+
+ std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
+
+ switch (ISD) {
+ case ISD::ADD:
+ if (ResTy->getScalarSizeInBits() == 2 * LT.second.getScalarSizeInBits())
+ // vwredsum and vwredsumu.
+ return (LT.first - 1) +
+ getArithmeticReductionCost(Instruction::Add, ValTy, FMF, CostKind);
+ break;
+ case ISD::FADD:
+ if (ResTy->getScalarSizeInBits() == 2 * LT.second.getScalarSizeInBits())
+ // vfwredosum and vfwredusum.
+ return (LT.first - 1) + getArithmeticReductionCost(Instruction::FAdd,
+ ValTy, FMF, CostKind);
+ break;
+ default:
+ break;
+ }
+ return BaseT::getExtendedReductionCost(Opcode, IsUnsigned, ResTy, ValTy, FMF,
+ CostKind);
+}
+
void RISCVTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
TTI::UnrollingPreferences &UP,
OptimizationRemarkEmitter *ORE) {
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