[PATCH] D130191: [RISCV] Teach ComputeNumSignBitsForTargetNode about Intrinsic::riscv_masked_cmpxchg_i64

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

In D130191#3666436 <https://reviews.llvm.org/D130191#3666436>, @jrtc27 wrote:

> Do we care about other masked i64 atomic intrinsics, and do the i32 ones ever see a benefit from implementing an equivalent?

I've added in the other masked i64 atomics, though was unable to produce examples where it makes a difference. Now I've fixed the logic error on the number of sign bits, there's no potential for benefit for the i32 ones (there would just be 1 mask bit after LR_W or atomicrmw_W of a native width value).


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https://reviews.llvm.org/D130191