[PATCH] D130191: [RISCV] Teach ComputeNumSignBitsForTargetNode about Intrinsic::riscv_masked_cmpxchg_i64

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 449237.
asb edited the summary of this revision.
asb added a comment.

Update to fix logic error regarding the sign bits (it's always just 33, the intrinsic doesn't to any masking itself. I improved the documentation on the intrinsics in 85c6fab <https://reviews.llvm.org/rG85c6fab8d317> which should help avoid such mistakes.

This update also lists all masked intrinsics, even though I've been unable to produce test cases for the others that lead to different codegen.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130191/new/

https://reviews.llvm.org/D130191

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
  llvm/test/CodeGen/RISCV/atomic-signext.ll


Index: llvm/test/CodeGen/RISCV/atomic-signext.ll
===================================================================
--- llvm/test/CodeGen/RISCV/atomic-signext.ll
+++ llvm/test/CodeGen/RISCV/atomic-signext.ll
@@ -3904,7 +3904,6 @@
 ; RV64IA-NEXT:    bnez a5, .LBB48_1
 ; RV64IA-NEXT:  .LBB48_3:
 ; RV64IA-NEXT:    and a0, a2, a4
-; RV64IA-NEXT:    sext.w a0, a0
 ; RV64IA-NEXT:    xor a0, a1, a0
 ; RV64IA-NEXT:    seqz a0, a0
 ; RV64IA-NEXT:    ret
@@ -4077,7 +4076,6 @@
 ; RV64IA-NEXT:    bnez a4, .LBB50_1
 ; RV64IA-NEXT:  .LBB50_3:
 ; RV64IA-NEXT:    and a0, a2, a5
-; RV64IA-NEXT:    sext.w a0, a0
 ; RV64IA-NEXT:    xor a0, a1, a0
 ; RV64IA-NEXT:    seqz a0, a0
 ; RV64IA-NEXT:    ret
Index: llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
===================================================================
--- llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
+++ llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
@@ -130,7 +130,6 @@
 ; RV64IA-NEXT:  .LBB2_5: # %do_cmpxchg
 ; RV64IA-NEXT:    # in Loop: Header=BB2_1 Depth=1
 ; RV64IA-NEXT:    and a4, a4, a0
-; RV64IA-NEXT:    sext.w a4, a4
 ; RV64IA-NEXT:    bne a1, a4, .LBB2_1
 ; RV64IA-NEXT:  # %bb.2: # %exit
 ; RV64IA-NEXT:    ret
@@ -207,7 +206,6 @@
 ; RV64IA-NEXT:  .LBB3_5: # %do_cmpxchg
 ; RV64IA-NEXT:    # in Loop: Header=BB3_1 Depth=1
 ; RV64IA-NEXT:    and a4, a4, a0
-; RV64IA-NEXT:    sext.w a4, a4
 ; RV64IA-NEXT:    beq a1, a4, .LBB3_1
 ; RV64IA-NEXT:  # %bb.2: # %exit
 ; RV64IA-NEXT:    ret
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9882,6 +9882,25 @@
       return XLen - EltBits + 1;
     break;
   }
+  case ISD::INTRINSIC_W_CHAIN: {
+    unsigned IntNo = Op.getConstantOperandVal(1);
+    switch (IntNo) {
+    default:
+      break;
+    case Intrinsic::riscv_masked_atomicrmw_xchg_i64:
+    case Intrinsic::riscv_masked_atomicrmw_add_i64:
+    case Intrinsic::riscv_masked_atomicrmw_sub_i64:
+    case Intrinsic::riscv_masked_atomicrmw_nand_i64:
+    case Intrinsic::riscv_masked_atomicrmw_max_i64:
+    case Intrinsic::riscv_masked_atomicrmw_min_i64:
+    case Intrinsic::riscv_masked_atomicrmw_umax_i64:
+    case Intrinsic::riscv_masked_atomicrmw_umin_i64:
+    case Intrinsic::riscv_masked_cmpxchg_i64:
+      // The return value of these intrinsics is produced by an LR_W or
+      // atomicrmw_W instruction and so is sign-extended from 32 bits.
+      return 33;
+    }
+  }
   }
 
   return 1;


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