[PATCH] D130783: [AMDGPU] Extend cases for ReadM0MovRelInterpHazard
Piotr Sobczak via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 1 09:02:53 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf29a19b0b8d2: [AMDGPU] Extend cases for ReadM0MovRelInterpHazard (authored by piotr).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D130783/new/
https://reviews.llvm.org/D130783
Files:
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
llvm/test/CodeGen/AMDGPU/hazard-lds-addtid.mir
Index: llvm/test/CodeGen/AMDGPU/hazard-lds-addtid.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/hazard-lds-addtid.mir
@@ -0,0 +1,50 @@
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,GFX9
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN
+---
+
+# GCN-LABEL: name: addtid
+
+# GCN-LABEL: bb.0:
+# GCN: S_MOV_B32
+# GFX9-NEXT: S_NOP
+# GCN-NEXT: DS_WRITE_ADDTID_B32
+
+# GCN-LABEL: bb.1:
+# GCN: S_MOV_B32
+# GFX9-NEXT: S_NOP
+# GCN-NEXT: DS_READ_ADDTID_B32
+
+# GCN-LABEL: bb.2:
+# GCN: S_MOV_B32
+# GFX9-NEXT: S_NOP
+# GCN-NEXT: DS_WRITE_ADDTID_B32
+
+# GCN-LABEL: bb.3:
+# GCN: S_MOV_B32
+# GFX9-NEXT: S_NOP
+# GCN-NEXT: DS_READ_ADDTID_B32
+
+name: addtid
+
+body: |
+ bb.0:
+ $m0 = S_MOV_B32 0
+ DS_WRITE_ADDTID_B32 killed $vgpr0, 0, 0, implicit $m0, implicit $exec
+ S_BRANCH %bb.1
+
+ bb.1:
+ $m0 = S_MOV_B32 0
+ $vgpr0 = DS_READ_ADDTID_B32 0, 0, implicit $m0, implicit $exec
+ S_BRANCH %bb.2
+
+ bb.2:
+ $m0 = S_MOV_B32 0
+ DS_WRITE_ADDTID_B32 killed $vgpr0, 0, 0, implicit $m0, implicit $exec
+ S_BRANCH %bb.3
+
+ bb.3:
+ $m0 = S_MOV_B32 0
+ $vgpr0 = DS_READ_ADDTID_B32 0, 0, implicit $m0, implicit $exec
+ S_ENDPGM 0
+...
Index: llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -232,7 +232,9 @@
return HazardType;
if (((ST.hasReadM0MovRelInterpHazard() &&
- (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode()))) ||
+ (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode()) ||
+ MI->getOpcode() == AMDGPU::DS_WRITE_ADDTID_B32 ||
+ MI->getOpcode() == AMDGPU::DS_READ_ADDTID_B32)) ||
(ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI)) ||
(ST.hasReadM0LdsDmaHazard() && isLdsDma(*MI)) ||
(ST.hasReadM0LdsDirectHazard() &&
@@ -357,7 +359,9 @@
return std::max(WaitStates, checkRFEHazards(MI));
if ((ST.hasReadM0MovRelInterpHazard() &&
- (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode()))) ||
+ (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode()) ||
+ MI->getOpcode() == AMDGPU::DS_WRITE_ADDTID_B32 ||
+ MI->getOpcode() == AMDGPU::DS_READ_ADDTID_B32)) ||
(ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI)) ||
(ST.hasReadM0LdsDmaHazard() && isLdsDma(*MI)) ||
(ST.hasReadM0LdsDirectHazard() && MI->readsRegister(AMDGPU::LDS_DIRECT)))
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