[llvm] f29a19b - [AMDGPU] Extend cases for ReadM0MovRelInterpHazard

[Piotr Sobczak via llvm-commits]

Author: Piotr Sobczak
Date: 2022-08-01T17:59:33+02:00
New Revision: f29a19b0b8d279616df795db52a3b6fafef6e1de

URL: https://github.com/llvm/llvm-project/commit/f29a19b0b8d279616df795db52a3b6fafef6e1de
DIFF: https://github.com/llvm/llvm-project/commit/f29a19b0b8d279616df795db52a3b6fafef6e1de.diff

LOG: [AMDGPU] Extend cases for ReadM0MovRelInterpHazard

Extend hazard recognizer of ReadM0MovRelInterpHazard with
DS_READ_ADDTID and DS_WRITE_ADDTID, as they also
require a manually inserted S_NOP after SALU writing m0.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D130783

Added: 
    llvm/test/CodeGen/AMDGPU/hazard-lds-addtid.mir

Modified: 
    llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index b6d16009e7769..481ecafd20ee7 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -232,7 +232,9 @@ GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
     return HazardType;
 
   if (((ST.hasReadM0MovRelInterpHazard() &&
-        (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode()))) ||
+        (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode()) ||
+         MI->getOpcode() == AMDGPU::DS_WRITE_ADDTID_B32 ||
+         MI->getOpcode() == AMDGPU::DS_READ_ADDTID_B32)) ||
        (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI)) ||
        (ST.hasReadM0LdsDmaHazard() && isLdsDma(*MI)) ||
        (ST.hasReadM0LdsDirectHazard() &&
@@ -357,7 +359,9 @@ unsigned GCNHazardRecognizer::PreEmitNoopsCommon(MachineInstr *MI) {
     return std::max(WaitStates, checkRFEHazards(MI));
 
   if ((ST.hasReadM0MovRelInterpHazard() &&
-       (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode()))) ||
+       (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode()) ||
+        MI->getOpcode() == AMDGPU::DS_WRITE_ADDTID_B32 ||
+        MI->getOpcode() == AMDGPU::DS_READ_ADDTID_B32)) ||
       (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI)) ||
       (ST.hasReadM0LdsDmaHazard() && isLdsDma(*MI)) ||
       (ST.hasReadM0LdsDirectHazard() && MI->readsRegister(AMDGPU::LDS_DIRECT)))

diff  --git a/llvm/test/CodeGen/AMDGPU/hazard-lds-addtid.mir b/llvm/test/CodeGen/AMDGPU/hazard-lds-addtid.mir
new file mode 100644
index 0000000000000..e9bb5dde1e4ab
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/hazard-lds-addtid.mir
@@ -0,0 +1,50 @@
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass post-RA-hazard-rec  %s -o - | FileCheck %s -check-prefixes=GCN,GFX9
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass post-RA-hazard-rec  %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass post-RA-hazard-rec  %s -o - | FileCheck %s -check-prefixes=GCN
+---
+
+# GCN-LABEL: name: addtid
+
+# GCN-LABEL: bb.0:
+# GCN: S_MOV_B32
+# GFX9-NEXT: S_NOP
+# GCN-NEXT: DS_WRITE_ADDTID_B32
+
+# GCN-LABEL: bb.1:
+# GCN: S_MOV_B32
+# GFX9-NEXT: S_NOP
+# GCN-NEXT: DS_READ_ADDTID_B32
+
+# GCN-LABEL: bb.2:
+# GCN: S_MOV_B32
+# GFX9-NEXT: S_NOP
+# GCN-NEXT: DS_WRITE_ADDTID_B32
+
+# GCN-LABEL: bb.3:
+# GCN: S_MOV_B32
+# GFX9-NEXT: S_NOP
+# GCN-NEXT: DS_READ_ADDTID_B32
+
+name: addtid
+
+body: |
+  bb.0:
+    $m0 = S_MOV_B32 0
+    DS_WRITE_ADDTID_B32 killed $vgpr0, 0, 0, implicit $m0, implicit $exec
+    S_BRANCH %bb.1
+
+  bb.1:
+    $m0 = S_MOV_B32 0
+    $vgpr0 = DS_READ_ADDTID_B32 0, 0, implicit $m0, implicit $exec
+    S_BRANCH %bb.2
+
+  bb.2:
+    $m0 = S_MOV_B32 0
+    DS_WRITE_ADDTID_B32 killed $vgpr0, 0, 0, implicit $m0, implicit $exec
+    S_BRANCH %bb.3
+
+  bb.3:
+    $m0 = S_MOV_B32 0
+    $vgpr0 = DS_READ_ADDTID_B32 0, 0, implicit $m0, implicit $exec
+    S_ENDPGM 0
+...