[PATCH] D130809: [RISCV] Explicitly select second operand of branch condition to X0.

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

LGTM as well.  I think this is worth taking, but as noted, I think we may have more oddities to dig into here.



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Comment at: llvm/test/CodeGen/RISCV/fpclamptosat.ll:3493
 ; RV32IFD-NEXT:    lw a3, 16(sp)
 ; RV32IFD-NEXT:    li a1, 0
 ; RV32IFD-NEXT:    beqz a0, .LBB46_3
----------------
I think there's still a problem with this code.  This initialization of a1 appears to never be clobbered, and yet we have multiple register copies below instead of zero initialization.  It's less immediate problematic than the branch interaction, but something odd is still going on here.  


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D130809/new/

https://reviews.llvm.org/D130809