[llvm] 3aae8cd - [AMDGPU][MC] Verify selection of LDS MUBUF opcodes
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 1 06:46:48 PDT 2022
Author: Dmitry Preobrazhensky
Date: 2022-08-01T16:44:39+03:00
New Revision: 3aae8cd8422dcd3ddaa1a6de146b18d8e9cd274f
URL: https://github.com/llvm/llvm-project/commit/3aae8cd8422dcd3ddaa1a6de146b18d8e9cd274f
DIFF: https://github.com/llvm/llvm-project/commit/3aae8cd8422dcd3ddaa1a6de146b18d8e9cd274f.diff
LOG: [AMDGPU][MC] Verify selection of LDS MUBUF opcodes
Differential Revision: https://reviews.llvm.org/D130761
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/test/MC/AMDGPU/gfx10_err_pos.s
llvm/test/MC/AMDGPU/gfx9-asm-err.s
llvm/test/MC/AMDGPU/gfx9_err_pos.s
llvm/test/MC/AMDGPU/mubuf.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 299ed1477c5c1..df0a53cb54850 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1650,8 +1650,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateDivScale(const MCInst &Inst);
bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
const SMLoc &IDLoc);
- bool validateFlatLdsDMA(const MCInst &Inst, const OperandVector &Operands,
- const SMLoc &IDLoc);
+ bool validateLdsDMA(uint64_t Enc, const MCInst &Inst,
+ const OperandVector &Operands, const SMLoc &IDLoc);
bool validateExeczVcczOperands(const OperandVector &Operands);
Optional<StringRef> validateLdsDirect(const MCInst &Inst);
unsigned getConstantBusLimit(unsigned Opcode) const;
@@ -4495,25 +4495,31 @@ bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
return true;
}
-bool AMDGPUAsmParser::validateFlatLdsDMA(const MCInst &Inst,
- const OperandVector &Operands,
- const SMLoc &IDLoc) {
- if (isGFX940())
+bool AMDGPUAsmParser::validateLdsDMA(uint64_t Enc, const MCInst &Inst,
+ const OperandVector &Operands,
+ const SMLoc &IDLoc) {
+ assert(Enc == SIInstrFlags::FLAT || Enc == SIInstrFlags::MUBUF);
+
+ // Exclude cases when there are separate DMA opcodes.
+ // In these cases, incorrect opcode selection is not possible.
+ if (Enc == SIInstrFlags::FLAT && isGFX940())
+ return true;
+ if (Enc == SIInstrFlags::MUBUF && isGFX11Plus())
return true;
uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
- if ((TSFlags & (SIInstrFlags::VALU | SIInstrFlags::FLAT)) !=
- (SIInstrFlags::VALU | SIInstrFlags::FLAT))
+ if ((TSFlags & (SIInstrFlags::VALU | Enc)) !=
+ (SIInstrFlags::VALU | Enc))
return true;
- // This is FLAT LDS DMA.
+ // This is FLAT/MUBUF LDS DMA.
SMLoc S = getImmLoc(AMDGPUOperand::ImmTyLDS, Operands);
StringRef CStr(S.getPointer());
if (!CStr.startswith("lds")) {
- // This is incorrectly selected LDS DMA version of a FLAT load opcode.
- // And LDS version should have 'lds' modifier, but it follows optional
- // operands so its absense is ignored by the matcher.
- Error(IDLoc, "invalid operands for instruction");
+ // This is incorrectly selected LDS DMA version of a FLAT/MUBUF load
+ // opcode. And LDS version should have 'lds' modifier, but it follows
+ // optional operands so its absense is ignored by the matcher.
+ Error(IDLoc, "missing dst operand or lds modifier");
return false;
}
@@ -4650,7 +4656,11 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
return false;
}
- if (!validateFlatLdsDMA(Inst, Operands, IDLoc)) {
+ if (!validateLdsDMA(SIInstrFlags::FLAT, Inst, Operands, IDLoc)) {
+ return false;
+ }
+
+ if (!validateLdsDMA(SIInstrFlags::MUBUF, Inst, Operands, IDLoc)) {
return false;
}
diff --git a/llvm/test/MC/AMDGPU/gfx10_err_pos.s b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
index 96580e674418c..5e26b07556374 100644
--- a/llvm/test/MC/AMDGPU/gfx10_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
@@ -989,6 +989,19 @@ s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0)
// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0)
// CHECK-NEXT:{{^}} ^
+//==============================================================================
+// missing dst operand or lds modifier
+
+buffer_load_dword off, s[8:11], s3
+// CHECK: error: missing dst operand or lds modifier
+// CHECK-NEXT:{{^}}buffer_load_dword off, s[8:11], s3
+// CHECK-NEXT:{{^}}^
+
+buffer_load_dword off, s[8:11], s3 offset:1
+// CHECK: error: missing dst operand or lds modifier
+// CHECK-NEXT:{{^}}buffer_load_dword off, s[8:11], s3 offset:1
+// CHECK-NEXT:{{^}}^
+
//==============================================================================
// missing message operation
diff --git a/llvm/test/MC/AMDGPU/gfx9-asm-err.s b/llvm/test/MC/AMDGPU/gfx9-asm-err.s
index a12fcdb742458..4842dbe576313 100644
--- a/llvm/test/MC/AMDGPU/gfx9-asm-err.s
+++ b/llvm/test/MC/AMDGPU/gfx9-asm-err.s
@@ -37,7 +37,7 @@ global_load_lds_dword v[2:3], off
// GFX9ERR: error: instruction not supported on this GPU
global_load_dword v[2:3], off
-// GFX9ERR: error: invalid operands for instruction
+// GFX9ERR: error: missing dst operand or lds modifier
scratch_load_dword v2, off, offset:256
-// GFX9ERR: error: invalid operands for instruction
+// GFX9ERR: error: missing dst operand or lds modifier
diff --git a/llvm/test/MC/AMDGPU/gfx9_err_pos.s b/llvm/test/MC/AMDGPU/gfx9_err_pos.s
index f6e696482ed9e..d91bd0fe3b9d3 100644
--- a/llvm/test/MC/AMDGPU/gfx9_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx9_err_pos.s
@@ -178,6 +178,19 @@ v_add_i16 v5, 0.5, v2
// CHECK-NEXT:{{^}}v_add_i16 v5, 0.5, v2
// CHECK-NEXT:{{^}} ^
+//==============================================================================
+// missing dst operand or lds modifier
+
+buffer_load_dword off, s[8:11], s3
+// CHECK: error: missing dst operand or lds modifier
+// CHECK-NEXT:{{^}}buffer_load_dword off, s[8:11], s3
+// CHECK-NEXT:{{^}}^
+
+buffer_load_dword off, s[8:11], s3 offset:1
+// CHECK: error: missing dst operand or lds modifier
+// CHECK-NEXT:{{^}}buffer_load_dword off, s[8:11], s3 offset:1
+// CHECK-NEXT:{{^}}^
+
//==============================================================================
// r128 modifier is not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/mubuf.s b/llvm/test/MC/AMDGPU/mubuf.s
index a1d972aabba04..7caecda3107ee 100644
--- a/llvm/test/MC/AMDGPU/mubuf.s
+++ b/llvm/test/MC/AMDGPU/mubuf.s
@@ -860,3 +860,9 @@ buffer_store_lds_dword s[4:7], s8 offset:4 lds tfe
buffer_store_lds_dword s[4:7], s8 offset:4 tfe lds
// NOSICI: error: instruction not supported on this GPU
// NOVI: error: invalid operand for instruction
+
+buffer_load_dword off, s[8:11], s3
+// NOSICIVI: error: missing dst operand or lds modifier
+
+buffer_load_dword off, s[8:11], s3 offset:1
+// NOSICIVI: error: missing dst operand or lds modifier
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