[llvm] a5a7a9d - [X86] Fix updating LiveVariables in convertToThreeAddress
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 1 05:52:24 PDT 2022
Author: Jay Foad
Date: 2022-08-01T13:45:21+01:00
New Revision: a5a7a9da39c0aeb67d5a3340e1345db42c6aaed4
URL: https://github.com/llvm/llvm-project/commit/a5a7a9da39c0aeb67d5a3340e1345db42c6aaed4
DIFF: https://github.com/llvm/llvm-project/commit/a5a7a9da39c0aeb67d5a3340e1345db42c6aaed4.diff
LOG: [X86] Fix updating LiveVariables in convertToThreeAddress
Fix all instances of:
*** Bad machine code: Kill missing from LiveVariables ***
in the X86 CodeGen tests with D129213 applied, which adds verification
of LiveIntervals after the TwoAddressInstruction pass runs.
Differential Revision: https://reviews.llvm.org/D129634
Added:
Modified:
llvm/lib/Target/X86/X86InstrInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 74ef831e1658a..4904e79f98703 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -1249,6 +1249,8 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
if (LV) {
// Update live variables.
LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
+ if (InRegLEA2)
+ LV->getVarInfo(InRegLEA2).Kills.push_back(NewMI);
LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
if (IsKill)
LV->replaceKillInstruction(Src, MI, *InsMI);
@@ -1337,6 +1339,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
bool Is64Bit = Subtarget.is64Bit();
bool Is8BitOp = false;
+ unsigned NumRegOperands = 2;
unsigned MIOpc = MI.getOpcode();
switch (MIOpc) {
default: llvm_unreachable("Unreachable!");
@@ -1385,6 +1388,9 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
MIB.add(ImplicitOp);
NewMI = MIB;
+ // Add kills if classifyLEAReg created a new register.
+ if (LV && SrcReg != Src.getReg())
+ LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
break;
}
case X86::SHL8ri:
@@ -1416,6 +1422,10 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
MIB.add(ImplicitOp);
NewMI = addOffset(MIB, 1);
+
+ // Add kills if classifyLEAReg created a new register.
+ if (LV && SrcReg != Src.getReg())
+ LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
break;
}
case X86::DEC64r:
@@ -1438,6 +1448,9 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
NewMI = addOffset(MIB, -1);
+ // Add kills if classifyLEAReg created a new register.
+ if (LV && SrcReg != Src.getReg())
+ LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
break;
}
case X86::DEC8r:
@@ -1485,8 +1498,15 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
MIB.add(ImplicitOp2);
NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
- if (LV && Src2.isKill())
- LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
+
+ // Add kills if classifyLEAReg created a new register.
+ if (LV) {
+ if (SrcReg2 != Src2.getReg())
+ LV->getVarInfo(SrcReg2).Kills.push_back(NewMI);
+ if (SrcReg != SrcReg2 && SrcReg != Src.getReg())
+ LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
+ }
+ NumRegOperands = 3;
break;
}
case X86::ADD8rr:
@@ -1525,6 +1545,10 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
MIB.add(ImplicitOp);
NewMI = addOffset(MIB, MI.getOperand(2));
+
+ // Add kills if classifyLEAReg created a new register.
+ if (LV && SrcReg != Src.getReg())
+ LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
break;
}
case X86::ADD8ri:
@@ -1729,6 +1753,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
.add(MI.getOperand(2))
.add(Src)
.add(MI.getOperand(3));
+ NumRegOperands = 4;
break;
}
}
@@ -1736,10 +1761,11 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
if (!NewMI) return nullptr;
if (LV) { // Update live variables
- if (Src.isKill())
- LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
- if (Dest.isDead())
- LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
+ for (unsigned I = 0; I < NumRegOperands; ++I) {
+ MachineOperand &Op = MI.getOperand(I);
+ if (Op.isDead() || Op.isKill())
+ LV->replaceKillInstruction(Op.getReg(), MI, *NewMI);
+ }
}
MachineBasicBlock &MBB = *MI.getParent();
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