[llvm] 260a641 - [RISCV] Pre-RA expand pseudos pass
Luís Marques via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 31 14:20:10 PDT 2022
Author: Luís Marques
Date: 2022-07-31T23:19:00+02:00
New Revision: 260a64106854986a981e49ed87ee740460a23eb5
URL: https://github.com/llvm/llvm-project/commit/260a64106854986a981e49ed87ee740460a23eb5
DIFF: https://github.com/llvm/llvm-project/commit/260a64106854986a981e49ed87ee740460a23eb5.diff
LOG: [RISCV] Pre-RA expand pseudos pass
Expand load address pseudo-instructions earlier (pre-ra) to allow follow-up
patches to fold the addi of PseudoLLA instructions into the immediate
operand of load/store instructions.
Differential Revision: https://reviews.llvm.org/D123264
Added:
Modified:
llvm/include/llvm/CodeGen/MachineInstr.h
llvm/lib/CodeGen/MachineInstr.cpp
llvm/lib/Target/RISCV/RISCV.h
llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/test/CodeGen/RISCV/O3-pipeline.ll
llvm/test/CodeGen/RISCV/codemodel-lowering.ll
llvm/test/CodeGen/RISCV/elf-preemption.ll
llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
llvm/test/CodeGen/RISCV/jumptable.ll
llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
llvm/test/CodeGen/RISCV/mir-target-flags.ll
llvm/test/CodeGen/RISCV/pic-models.ll
llvm/test/CodeGen/RISCV/tls-models.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index 5f483a8d0312c..11e4817a87b8c 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -923,6 +923,8 @@ class MachineInstr
/// For example, if the instruction has a unique labels attached
/// to it, duplicating it would cause multiple definition errors.
bool isNotDuplicable(QueryType Type = AnyInBundle) const {
+ if (getPreInstrSymbol() || getPostInstrSymbol())
+ return true;
return hasProperty(MCID::NotDuplicable, Type);
}
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index e92dec5bea489..2321a273c030c 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -630,6 +630,11 @@ bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
if (getDebugLoc() && Other.getDebugLoc() &&
getDebugLoc() != Other.getDebugLoc())
return false;
+ // If pre- or post-instruction symbols do not match then the two instructions
+ // are not identical.
+ if (getPreInstrSymbol() != Other.getPreInstrSymbol() ||
+ getPostInstrSymbol() != Other.getPostInstrSymbol())
+ return false;
return true;
}
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index e6140edc8403a..6b4493eee1604 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -56,6 +56,9 @@ void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
FunctionPass *createRISCVExpandPseudoPass();
void initializeRISCVExpandPseudoPass(PassRegistry &);
+FunctionPass *createRISCVPreRAExpandPseudoPass();
+void initializeRISCVPreRAExpandPseudoPass(PassRegistry &);
+
FunctionPass *createRISCVExpandAtomicPseudoPass();
void initializeRISCVExpandAtomicPseudoPass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index e4e01d9f6f2f4..b5d5ffee7b857 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -19,10 +19,12 @@
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/MC/MCContext.h"
using namespace llvm;
#define RISCV_EXPAND_PSEUDO_NAME "RISCV pseudo instruction expansion pass"
+#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISCV Pre-RA pseudo instruction expansion pass"
namespace {
@@ -43,22 +45,6 @@ class RISCVExpandPseudo : public MachineFunctionPass {
bool expandMBB(MachineBasicBlock &MBB);
bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI);
- bool expandAuipcInstPair(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI,
- unsigned FlagsHi, unsigned SecondOpcode);
- bool expandLoadLocalAddress(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
- bool expandLoadAddress(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
- bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
- bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
bool expandVSetVL(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, unsigned Opcode);
@@ -96,14 +82,6 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
// expanded instructions for each pseudo is correct in the Size field of the
// tablegen definition for the pseudo.
switch (MBBI->getOpcode()) {
- case RISCV::PseudoLLA:
- return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
- case RISCV::PseudoLA:
- return expandLoadAddress(MBB, MBBI, NextMBBI);
- case RISCV::PseudoLA_TLS_IE:
- return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
- case RISCV::PseudoLA_TLS_GD:
- return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
case RISCV::PseudoVSETVLI:
case RISCV::PseudoVSETVLIX0:
case RISCV::PseudoVSETIVLI:
@@ -155,90 +133,6 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
return false;
}
-bool RISCVExpandPseudo::expandAuipcInstPair(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
- unsigned SecondOpcode) {
- MachineFunction *MF = MBB.getParent();
- MachineInstr &MI = *MBBI;
- DebugLoc DL = MI.getDebugLoc();
-
- Register DestReg = MI.getOperand(0).getReg();
- const MachineOperand &Symbol = MI.getOperand(1);
-
- MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-
- // Tell AsmPrinter that we unconditionally want the symbol of this label to be
- // emitted.
- NewMBB->setLabelMustBeEmitted();
-
- MF->insert(++MBB.getIterator(), NewMBB);
-
- BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg)
- .addDisp(Symbol, 0, FlagsHi);
- BuildMI(NewMBB, DL, TII->get(SecondOpcode), DestReg)
- .addReg(DestReg)
- .addMBB(NewMBB, RISCVII::MO_PCREL_LO);
-
- // Move all the rest of the instructions to NewMBB.
- NewMBB->splice(NewMBB->end(), &MBB, std::next(MBBI), MBB.end());
- // Update machine-CFG edges.
- NewMBB->transferSuccessorsAndUpdatePHIs(&MBB);
- // Make the original basic block fall-through to the new.
- MBB.addSuccessor(NewMBB);
-
- // Make sure live-ins are correctly attached to this new basic block.
- LivePhysRegs LiveRegs;
- computeAndAddLiveIns(LiveRegs, *NewMBB);
-
- NextMBBI = MBB.end();
- MI.eraseFromParent();
- return true;
-}
-
-bool RISCVExpandPseudo::expandLoadLocalAddress(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
- return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
- RISCV::ADDI);
-}
-
-bool RISCVExpandPseudo::expandLoadAddress(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
- MachineFunction *MF = MBB.getParent();
-
- unsigned SecondOpcode;
- unsigned FlagsHi;
- if (MF->getTarget().isPositionIndependent()) {
- const auto &STI = MF->getSubtarget<RISCVSubtarget>();
- SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
- FlagsHi = RISCVII::MO_GOT_HI;
- } else {
- SecondOpcode = RISCV::ADDI;
- FlagsHi = RISCVII::MO_PCREL_HI;
- }
- return expandAuipcInstPair(MBB, MBBI, NextMBBI, FlagsHi, SecondOpcode);
-}
-
-bool RISCVExpandPseudo::expandLoadTLSIEAddress(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
- MachineFunction *MF = MBB.getParent();
-
- const auto &STI = MF->getSubtarget<RISCVSubtarget>();
- unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
- return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
- SecondOpcode);
-}
-
-bool RISCVExpandPseudo::expandLoadTLSGDAddress(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
- return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
- RISCV::ADDI);
-}
-
bool RISCVExpandPseudo::expandVSetVL(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) {
assert(MBBI->getNumExplicitOperands() == 3 && MBBI->getNumOperands() >= 5 &&
@@ -377,12 +271,167 @@ bool RISCVExpandPseudo::expandVRELOAD(MachineBasicBlock &MBB,
return true;
}
+class RISCVPreRAExpandPseudo : public MachineFunctionPass {
+public:
+ const RISCVInstrInfo *TII;
+ static char ID;
+
+ RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {
+ initializeRISCVPreRAExpandPseudoPass(*PassRegistry::getPassRegistry());
+ }
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesCFG();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+ StringRef getPassName() const override {
+ return RISCV_PRERA_EXPAND_PSEUDO_NAME;
+ }
+
+private:
+ bool expandMBB(MachineBasicBlock &MBB);
+ bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+ bool expandAuipcInstPair(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI,
+ unsigned FlagsHi, unsigned SecondOpcode);
+ bool expandLoadLocalAddress(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+ bool expandLoadAddress(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+ bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+ bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
+};
+
+char RISCVPreRAExpandPseudo::ID = 0;
+
+bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
+ TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
+ bool Modified = false;
+ for (auto &MBB : MF)
+ Modified |= expandMBB(MBB);
+ return Modified;
+}
+
+bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
+ bool Modified = false;
+
+ MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
+ while (MBBI != E) {
+ MachineBasicBlock::iterator NMBBI = std::next(MBBI);
+ Modified |= expandMI(MBB, MBBI, NMBBI);
+ MBBI = NMBBI;
+ }
+
+ return Modified;
+}
+
+bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+
+ switch (MBBI->getOpcode()) {
+ case RISCV::PseudoLLA:
+ return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
+ case RISCV::PseudoLA:
+ return expandLoadAddress(MBB, MBBI, NextMBBI);
+ case RISCV::PseudoLA_TLS_IE:
+ return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
+ case RISCV::PseudoLA_TLS_GD:
+ return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
+ }
+ return false;
+}
+
+bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
+ unsigned SecondOpcode) {
+ MachineFunction *MF = MBB.getParent();
+ MachineInstr &MI = *MBBI;
+ DebugLoc DL = MI.getDebugLoc();
+
+ Register DestReg = MI.getOperand(0).getReg();
+ Register ScratchReg =
+ MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
+
+ MachineOperand &Symbol = MI.getOperand(1);
+ Symbol.setTargetFlags(FlagsHi);
+ MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
+
+ MachineInstr *MIAUIPC =
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
+ MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
+
+ MachineInstr *SecondMI =
+ BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
+ .addReg(ScratchReg)
+ .addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
+
+ if (MI.hasOneMemOperand())
+ SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
+
+ MI.eraseFromParent();
+ return true;
+}
+
+bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+ return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
+ RISCV::ADDI);
+}
+
+bool RISCVPreRAExpandPseudo::expandLoadAddress(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+ MachineFunction *MF = MBB.getParent();
+
+ assert(MF->getTarget().isPositionIndependent());
+ const auto &STI = MF->getSubtarget<RISCVSubtarget>();
+ unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
+ return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
+ SecondOpcode);
+}
+
+bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+ MachineFunction *MF = MBB.getParent();
+
+ const auto &STI = MF->getSubtarget<RISCVSubtarget>();
+ unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
+ return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
+ SecondOpcode);
+}
+
+bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+ return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
+ RISCV::ADDI);
+}
+
} // end of anonymous namespace
INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
RISCV_EXPAND_PSEUDO_NAME, false, false)
+
+INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
+ RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
+
namespace llvm {
FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
+FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
} // end of namespace llvm
diff --git a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
index c457a95544cf6..281918259cdb3 100644
--- a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
@@ -125,6 +125,9 @@ bool llvm::lowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
case MachineOperand::MO_JumpTableIndex:
MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP);
break;
+ case MachineOperand::MO_MCSymbol:
+ MCOp = lowerSymbolOperand(MO, MO.getMCSymbol(), AP);
+ break;
}
return true;
}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 50fcb00e6c63b..f97b82d8fa0bf 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -52,6 +52,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVCodeGenPreparePass(*PR);
initializeRISCVMergeBaseOffsetOptPass(*PR);
initializeRISCVSExtWRemovalPass(*PR);
+ initializeRISCVPreRAExpandPseudoPass(*PR);
initializeRISCVExpandPseudoPass(*PR);
initializeRISCVInsertVSETVLIPass(*PR);
}
@@ -253,6 +254,7 @@ void RISCVPassConfig::addMachineSSAOptimization() {
if (TM->getTargetTriple().getArch() == Triple::riscv64)
addPass(createRISCVSExtWRemovalPass());
+ addPass(createRISCVPreRAExpandPseudoPass());
}
void RISCVPassConfig::addPreRegAlloc() {
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
index a2e6bb7a13540..33b5257e1bc6e 100644
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -96,6 +96,7 @@
; CHECK-NEXT: Peephole Optimizations
; CHECK-NEXT: Remove dead machine instructions
; RV64-NEXT: RISCV sext.w Removal
+; CHECK-NEXT: RISCV Pre-RA pseudo instruction expansion pass
; CHECK-NEXT: RISCV Merge Base Offset
; CHECK-NEXT: RISCV Insert VSETVLI pass
; CHECK-NEXT: Detect Dead Lanes
diff --git a/llvm/test/CodeGen/RISCV/codemodel-lowering.ll b/llvm/test/CodeGen/RISCV/codemodel-lowering.ll
index d2ae4e6d0f94a..cfd028e508032 100644
--- a/llvm/test/CodeGen/RISCV/codemodel-lowering.ll
+++ b/llvm/test/CodeGen/RISCV/codemodel-lowering.ll
@@ -16,9 +16,9 @@ define i32 @lower_global(i32 %a) nounwind {
;
; RV32I-MEDIUM-LABEL: lower_global:
; RV32I-MEDIUM: # %bb.0:
-; RV32I-MEDIUM-NEXT: .LBB0_1: # Label of block must be emitted
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi0:
; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(G)
-; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB0_1)
+; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi0)
; RV32I-MEDIUM-NEXT: lw a0, 0(a0)
; RV32I-MEDIUM-NEXT: ret
%1 = load volatile i32, i32* @G
@@ -39,9 +39,9 @@ define void @lower_blockaddress() nounwind {
;
; RV32I-MEDIUM-LABEL: lower_blockaddress:
; RV32I-MEDIUM: # %bb.0:
-; RV32I-MEDIUM-NEXT: .LBB1_1: # Label of block must be emitted
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi1:
; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(addr)
-; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB1_1)
+; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi1)
; RV32I-MEDIUM-NEXT: li a1, 1
; RV32I-MEDIUM-NEXT: sw a1, 0(a0)
; RV32I-MEDIUM-NEXT: ret
@@ -79,10 +79,9 @@ define signext i32 @lower_blockaddress_displ(i32 signext %w) nounwind {
; RV32I-MEDIUM-LABEL: lower_blockaddress_displ:
; RV32I-MEDIUM: # %bb.0: # %entry
; RV32I-MEDIUM-NEXT: addi sp, sp, -16
-; RV32I-MEDIUM-NEXT: .LBB2_4: # %entry
-; RV32I-MEDIUM-NEXT: # Label of block must be emitted
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi2:
; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.Ltmp0)
-; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB2_4)
+; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi2)
; RV32I-MEDIUM-NEXT: li a2, 101
; RV32I-MEDIUM-NEXT: sw a1, 8(sp)
; RV32I-MEDIUM-NEXT: blt a0, a2, .LBB2_3
@@ -134,9 +133,9 @@ define float @lower_constantpool(float %a) nounwind {
;
; RV32I-MEDIUM-LABEL: lower_constantpool:
; RV32I-MEDIUM: # %bb.0:
-; RV32I-MEDIUM-NEXT: .LBB3_1: # Label of block must be emitted
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi3:
; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(.LCPI3_0)
-; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB3_1)
+; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi3)
; RV32I-MEDIUM-NEXT: flw ft0, 0(a0)
; RV32I-MEDIUM-NEXT: fadd.s fa0, fa0, ft0
; RV32I-MEDIUM-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/elf-preemption.ll b/llvm/test/CodeGen/RISCV/elf-preemption.ll
index 11f8736d1d14e..9a39fa050981c 100644
--- a/llvm/test/CodeGen/RISCV/elf-preemption.ll
+++ b/llvm/test/CodeGen/RISCV/elf-preemption.ll
@@ -18,9 +18,9 @@ define i32* @get_preemptable_var() nounwind {
;
; RV32-PIC-LABEL: get_preemptable_var:
; RV32-PIC: # %bb.0:
-; RV32-PIC-NEXT: .LBB0_1: # Label of block must be emitted
+; RV32-PIC-NEXT: .Lpcrel_hi0:
; RV32-PIC-NEXT: auipc a0, %got_pcrel_hi(preemptable_var)
-; RV32-PIC-NEXT: lw a0, %pcrel_lo(.LBB0_1)(a0)
+; RV32-PIC-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi0)(a0)
; RV32-PIC-NEXT: ret
;
; RV64-STATIC-LABEL: get_preemptable_var:
@@ -31,9 +31,9 @@ define i32* @get_preemptable_var() nounwind {
;
; RV64-PIC-LABEL: get_preemptable_var:
; RV64-PIC: # %bb.0:
-; RV64-PIC-NEXT: .LBB0_1: # Label of block must be emitted
+; RV64-PIC-NEXT: .Lpcrel_hi0:
; RV64-PIC-NEXT: auipc a0, %got_pcrel_hi(preemptable_var)
-; RV64-PIC-NEXT: ld a0, %pcrel_lo(.LBB0_1)(a0)
+; RV64-PIC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi0)(a0)
; RV64-PIC-NEXT: ret
ret i32* @preemptable_var
}
@@ -48,9 +48,9 @@ define i32* @get_dsolocal_var() nounwind {
;
; RV32-PIC-LABEL: get_dsolocal_var:
; RV32-PIC: # %bb.0:
-; RV32-PIC-NEXT: .LBB1_1: # Label of block must be emitted
+; RV32-PIC-NEXT: .Lpcrel_hi1:
; RV32-PIC-NEXT: auipc a0, %pcrel_hi(.Ldsolocal_var$local)
-; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB1_1)
+; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi1)
; RV32-PIC-NEXT: ret
;
; RV64-STATIC-LABEL: get_dsolocal_var:
@@ -61,9 +61,9 @@ define i32* @get_dsolocal_var() nounwind {
;
; RV64-PIC-LABEL: get_dsolocal_var:
; RV64-PIC: # %bb.0:
-; RV64-PIC-NEXT: .LBB1_1: # Label of block must be emitted
+; RV64-PIC-NEXT: .Lpcrel_hi1:
; RV64-PIC-NEXT: auipc a0, %pcrel_hi(.Ldsolocal_var$local)
-; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB1_1)
+; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi1)
; RV64-PIC-NEXT: ret
ret i32* @dsolocal_var
}
@@ -78,9 +78,9 @@ define i32* @get_weak_dsolocal_var() nounwind {
;
; RV32-PIC-LABEL: get_weak_dsolocal_var:
; RV32-PIC: # %bb.0:
-; RV32-PIC-NEXT: .LBB2_1: # Label of block must be emitted
+; RV32-PIC-NEXT: .Lpcrel_hi2:
; RV32-PIC-NEXT: auipc a0, %pcrel_hi(weak_dsolocal_var)
-; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB2_1)
+; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi2)
; RV32-PIC-NEXT: ret
;
; RV64-STATIC-LABEL: get_weak_dsolocal_var:
@@ -91,9 +91,9 @@ define i32* @get_weak_dsolocal_var() nounwind {
;
; RV64-PIC-LABEL: get_weak_dsolocal_var:
; RV64-PIC: # %bb.0:
-; RV64-PIC-NEXT: .LBB2_1: # Label of block must be emitted
+; RV64-PIC-NEXT: .Lpcrel_hi2:
; RV64-PIC-NEXT: auipc a0, %pcrel_hi(weak_dsolocal_var)
-; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB2_1)
+; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi2)
; RV64-PIC-NEXT: ret
ret i32* @weak_dsolocal_var
}
@@ -108,9 +108,9 @@ define i32* @get_hidden_var() nounwind {
;
; RV32-PIC-LABEL: get_hidden_var:
; RV32-PIC: # %bb.0:
-; RV32-PIC-NEXT: .LBB3_1: # Label of block must be emitted
+; RV32-PIC-NEXT: .Lpcrel_hi3:
; RV32-PIC-NEXT: auipc a0, %pcrel_hi(hidden_var)
-; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB3_1)
+; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi3)
; RV32-PIC-NEXT: ret
;
; RV64-STATIC-LABEL: get_hidden_var:
@@ -121,9 +121,9 @@ define i32* @get_hidden_var() nounwind {
;
; RV64-PIC-LABEL: get_hidden_var:
; RV64-PIC: # %bb.0:
-; RV64-PIC-NEXT: .LBB3_1: # Label of block must be emitted
+; RV64-PIC-NEXT: .Lpcrel_hi3:
; RV64-PIC-NEXT: auipc a0, %pcrel_hi(hidden_var)
-; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB3_1)
+; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi3)
; RV64-PIC-NEXT: ret
ret i32* @hidden_var
}
@@ -138,9 +138,9 @@ define i32* @get_protected_var() nounwind {
;
; RV32-PIC-LABEL: get_protected_var:
; RV32-PIC: # %bb.0:
-; RV32-PIC-NEXT: .LBB4_1: # Label of block must be emitted
+; RV32-PIC-NEXT: .Lpcrel_hi4:
; RV32-PIC-NEXT: auipc a0, %pcrel_hi(protected_var)
-; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB4_1)
+; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi4)
; RV32-PIC-NEXT: ret
;
; RV64-STATIC-LABEL: get_protected_var:
@@ -151,9 +151,9 @@ define i32* @get_protected_var() nounwind {
;
; RV64-PIC-LABEL: get_protected_var:
; RV64-PIC: # %bb.0:
-; RV64-PIC-NEXT: .LBB4_1: # Label of block must be emitted
+; RV64-PIC-NEXT: .Lpcrel_hi4:
; RV64-PIC-NEXT: auipc a0, %pcrel_hi(protected_var)
-; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB4_1)
+; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi4)
; RV64-PIC-NEXT: ret
ret i32* @protected_var
}
@@ -167,9 +167,9 @@ define dso_preemptable void()* @preemptable_func() nounwind {
;
; RV32-PIC-LABEL: preemptable_func:
; RV32-PIC: # %bb.0:
-; RV32-PIC-NEXT: .LBB5_1: # Label of block must be emitted
+; RV32-PIC-NEXT: .Lpcrel_hi5:
; RV32-PIC-NEXT: auipc a0, %got_pcrel_hi(preemptable_func)
-; RV32-PIC-NEXT: lw a0, %pcrel_lo(.LBB5_1)(a0)
+; RV32-PIC-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi5)(a0)
; RV32-PIC-NEXT: ret
;
; RV64-STATIC-LABEL: preemptable_func:
@@ -180,9 +180,9 @@ define dso_preemptable void()* @preemptable_func() nounwind {
;
; RV64-PIC-LABEL: preemptable_func:
; RV64-PIC: # %bb.0:
-; RV64-PIC-NEXT: .LBB5_1: # Label of block must be emitted
+; RV64-PIC-NEXT: .Lpcrel_hi5:
; RV64-PIC-NEXT: auipc a0, %got_pcrel_hi(preemptable_func)
-; RV64-PIC-NEXT: ld a0, %pcrel_lo(.LBB5_1)(a0)
+; RV64-PIC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi5)(a0)
; RV64-PIC-NEXT: ret
ret void()* bitcast(void()*()* @preemptable_func to void()*)
}
@@ -196,9 +196,9 @@ define dso_local void()* @dsolocal_func() nounwind {
;
; RV32-PIC-LABEL: dsolocal_func:
; RV32-PIC: # %bb.0:
-; RV32-PIC-NEXT: .LBB6_1: # Label of block must be emitted
+; RV32-PIC-NEXT: .Lpcrel_hi6:
; RV32-PIC-NEXT: auipc a0, %pcrel_hi(.Ldsolocal_func$local)
-; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB6_1)
+; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi6)
; RV32-PIC-NEXT: ret
;
; RV64-STATIC-LABEL: dsolocal_func:
@@ -209,9 +209,9 @@ define dso_local void()* @dsolocal_func() nounwind {
;
; RV64-PIC-LABEL: dsolocal_func:
; RV64-PIC: # %bb.0:
-; RV64-PIC-NEXT: .LBB6_1: # Label of block must be emitted
+; RV64-PIC-NEXT: .Lpcrel_hi6:
; RV64-PIC-NEXT: auipc a0, %pcrel_hi(.Ldsolocal_func$local)
-; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB6_1)
+; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi6)
; RV64-PIC-NEXT: ret
ret void()* bitcast(void()*()* @dsolocal_func to void()*)
}
@@ -225,9 +225,9 @@ define weak dso_local void()* @weak_dsolocal_func() nounwind {
;
; RV32-PIC-LABEL: weak_dsolocal_func:
; RV32-PIC: # %bb.0:
-; RV32-PIC-NEXT: .LBB7_1: # Label of block must be emitted
+; RV32-PIC-NEXT: .Lpcrel_hi7:
; RV32-PIC-NEXT: auipc a0, %pcrel_hi(weak_dsolocal_func)
-; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB7_1)
+; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi7)
; RV32-PIC-NEXT: ret
;
; RV64-STATIC-LABEL: weak_dsolocal_func:
@@ -238,9 +238,9 @@ define weak dso_local void()* @weak_dsolocal_func() nounwind {
;
; RV64-PIC-LABEL: weak_dsolocal_func:
; RV64-PIC: # %bb.0:
-; RV64-PIC-NEXT: .LBB7_1: # Label of block must be emitted
+; RV64-PIC-NEXT: .Lpcrel_hi7:
; RV64-PIC-NEXT: auipc a0, %pcrel_hi(weak_dsolocal_func)
-; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB7_1)
+; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi7)
; RV64-PIC-NEXT: ret
ret void()* bitcast(void()*()* @weak_dsolocal_func to void()*)
}
diff --git a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
index 25c232d489785..49cd799824ff8 100644
--- a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
+++ b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
@@ -32,10 +32,9 @@ define dso_local i64 @load_g_0() nounwind {
;
; RV32I-MEDIUM-LABEL: load_g_0:
; RV32I-MEDIUM: # %bb.0: # %entry
-; RV32I-MEDIUM-NEXT: .LBB0_1: # %entry
-; RV32I-MEDIUM-NEXT: # Label of block must be emitted
-; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(g_0)
-; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB0_1)
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi0:
+; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_0)
+; RV32I-MEDIUM-NEXT: addi a1, a0, %pcrel_lo(.Lpcrel_hi0)
; RV32I-MEDIUM-NEXT: lw a0, 0(a1)
; RV32I-MEDIUM-NEXT: lw a1, 4(a1)
; RV32I-MEDIUM-NEXT: ret
@@ -48,10 +47,9 @@ define dso_local i64 @load_g_0() nounwind {
;
; RV64I-MEDIUM-LABEL: load_g_0:
; RV64I-MEDIUM: # %bb.0: # %entry
-; RV64I-MEDIUM-NEXT: .LBB0_1: # %entry
-; RV64I-MEDIUM-NEXT: # Label of block must be emitted
+; RV64I-MEDIUM-NEXT: .Lpcrel_hi0:
; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_0)
-; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB0_1)
+; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi0)
; RV64I-MEDIUM-NEXT: ld a0, 0(a0)
; RV64I-MEDIUM-NEXT: ret
entry:
@@ -70,10 +68,9 @@ define dso_local i64 @load_g_1() nounwind {
;
; RV32I-MEDIUM-LABEL: load_g_1:
; RV32I-MEDIUM: # %bb.0: # %entry
-; RV32I-MEDIUM-NEXT: .LBB1_1: # %entry
-; RV32I-MEDIUM-NEXT: # Label of block must be emitted
-; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(g_1)
-; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB1_1)
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi1:
+; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_1)
+; RV32I-MEDIUM-NEXT: addi a1, a0, %pcrel_lo(.Lpcrel_hi1)
; RV32I-MEDIUM-NEXT: lw a0, 0(a1)
; RV32I-MEDIUM-NEXT: lw a1, 4(a1)
; RV32I-MEDIUM-NEXT: ret
@@ -86,10 +83,9 @@ define dso_local i64 @load_g_1() nounwind {
;
; RV64I-MEDIUM-LABEL: load_g_1:
; RV64I-MEDIUM: # %bb.0: # %entry
-; RV64I-MEDIUM-NEXT: .LBB1_1: # %entry
-; RV64I-MEDIUM-NEXT: # Label of block must be emitted
+; RV64I-MEDIUM-NEXT: .Lpcrel_hi1:
; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_1)
-; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB1_1)
+; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi1)
; RV64I-MEDIUM-NEXT: ld a0, 0(a0)
; RV64I-MEDIUM-NEXT: ret
entry:
@@ -108,10 +104,9 @@ define dso_local i64 @load_g_2() nounwind {
;
; RV32I-MEDIUM-LABEL: load_g_2:
; RV32I-MEDIUM: # %bb.0: # %entry
-; RV32I-MEDIUM-NEXT: .LBB2_1: # %entry
-; RV32I-MEDIUM-NEXT: # Label of block must be emitted
-; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(g_2)
-; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB2_1)
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi2:
+; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_2)
+; RV32I-MEDIUM-NEXT: addi a1, a0, %pcrel_lo(.Lpcrel_hi2)
; RV32I-MEDIUM-NEXT: lw a0, 0(a1)
; RV32I-MEDIUM-NEXT: lw a1, 4(a1)
; RV32I-MEDIUM-NEXT: ret
@@ -124,10 +119,9 @@ define dso_local i64 @load_g_2() nounwind {
;
; RV64I-MEDIUM-LABEL: load_g_2:
; RV64I-MEDIUM: # %bb.0: # %entry
-; RV64I-MEDIUM-NEXT: .LBB2_1: # %entry
-; RV64I-MEDIUM-NEXT: # Label of block must be emitted
+; RV64I-MEDIUM-NEXT: .Lpcrel_hi2:
; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_2)
-; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB2_1)
+; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi2)
; RV64I-MEDIUM-NEXT: ld a0, 0(a0)
; RV64I-MEDIUM-NEXT: ret
entry:
@@ -146,10 +140,9 @@ define dso_local i64 @load_g_4() nounwind {
;
; RV32I-MEDIUM-LABEL: load_g_4:
; RV32I-MEDIUM: # %bb.0: # %entry
-; RV32I-MEDIUM-NEXT: .LBB3_1: # %entry
-; RV32I-MEDIUM-NEXT: # Label of block must be emitted
-; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(g_4)
-; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB3_1)
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi3:
+; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_4)
+; RV32I-MEDIUM-NEXT: addi a1, a0, %pcrel_lo(.Lpcrel_hi3)
; RV32I-MEDIUM-NEXT: lw a0, 0(a1)
; RV32I-MEDIUM-NEXT: lw a1, 4(a1)
; RV32I-MEDIUM-NEXT: ret
@@ -162,10 +155,9 @@ define dso_local i64 @load_g_4() nounwind {
;
; RV64I-MEDIUM-LABEL: load_g_4:
; RV64I-MEDIUM: # %bb.0: # %entry
-; RV64I-MEDIUM-NEXT: .LBB3_1: # %entry
-; RV64I-MEDIUM-NEXT: # Label of block must be emitted
+; RV64I-MEDIUM-NEXT: .Lpcrel_hi3:
; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_4)
-; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB3_1)
+; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi3)
; RV64I-MEDIUM-NEXT: ld a0, 0(a0)
; RV64I-MEDIUM-NEXT: ret
entry:
@@ -183,10 +175,9 @@ define dso_local i64 @load_g_8() nounwind {
;
; RV32I-MEDIUM-LABEL: load_g_8:
; RV32I-MEDIUM: # %bb.0: # %entry
-; RV32I-MEDIUM-NEXT: .LBB4_1: # %entry
-; RV32I-MEDIUM-NEXT: # Label of block must be emitted
-; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(g_8)
-; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB4_1)
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi4:
+; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_8)
+; RV32I-MEDIUM-NEXT: addi a1, a0, %pcrel_lo(.Lpcrel_hi4)
; RV32I-MEDIUM-NEXT: lw a0, 0(a1)
; RV32I-MEDIUM-NEXT: lw a1, 4(a1)
; RV32I-MEDIUM-NEXT: ret
@@ -199,10 +190,9 @@ define dso_local i64 @load_g_8() nounwind {
;
; RV64I-MEDIUM-LABEL: load_g_8:
; RV64I-MEDIUM: # %bb.0: # %entry
-; RV64I-MEDIUM-NEXT: .LBB4_1: # %entry
-; RV64I-MEDIUM-NEXT: # Label of block must be emitted
+; RV64I-MEDIUM-NEXT: .Lpcrel_hi4:
; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_8)
-; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB4_1)
+; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi4)
; RV64I-MEDIUM-NEXT: ld a0, 0(a0)
; RV64I-MEDIUM-NEXT: ret
entry:
@@ -220,10 +210,9 @@ define dso_local i64 @load_g_16() nounwind {
;
; RV32I-MEDIUM-LABEL: load_g_16:
; RV32I-MEDIUM: # %bb.0: # %entry
-; RV32I-MEDIUM-NEXT: .LBB5_1: # %entry
-; RV32I-MEDIUM-NEXT: # Label of block must be emitted
-; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(g_16)
-; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB5_1)
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi5:
+; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_16)
+; RV32I-MEDIUM-NEXT: addi a1, a0, %pcrel_lo(.Lpcrel_hi5)
; RV32I-MEDIUM-NEXT: lw a0, 0(a1)
; RV32I-MEDIUM-NEXT: lw a1, 4(a1)
; RV32I-MEDIUM-NEXT: ret
@@ -236,10 +225,9 @@ define dso_local i64 @load_g_16() nounwind {
;
; RV64I-MEDIUM-LABEL: load_g_16:
; RV64I-MEDIUM: # %bb.0: # %entry
-; RV64I-MEDIUM-NEXT: .LBB5_1: # %entry
-; RV64I-MEDIUM-NEXT: # Label of block must be emitted
+; RV64I-MEDIUM-NEXT: .Lpcrel_hi5:
; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_16)
-; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB5_1)
+; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi5)
; RV64I-MEDIUM-NEXT: ld a0, 0(a0)
; RV64I-MEDIUM-NEXT: ret
entry:
@@ -258,10 +246,9 @@ define dso_local void @store_g_4() nounwind {
;
; RV32I-MEDIUM-LABEL: store_g_4:
; RV32I-MEDIUM: # %bb.0: # %entry
-; RV32I-MEDIUM-NEXT: .LBB6_1: # %entry
-; RV32I-MEDIUM-NEXT: # Label of block must be emitted
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi6:
; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_4)
-; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB6_1)
+; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi6)
; RV32I-MEDIUM-NEXT: sw zero, 4(a0)
; RV32I-MEDIUM-NEXT: sw zero, 0(a0)
; RV32I-MEDIUM-NEXT: ret
@@ -274,10 +261,9 @@ define dso_local void @store_g_4() nounwind {
;
; RV64I-MEDIUM-LABEL: store_g_4:
; RV64I-MEDIUM: # %bb.0: # %entry
-; RV64I-MEDIUM-NEXT: .LBB6_1: # %entry
-; RV64I-MEDIUM-NEXT: # Label of block must be emitted
+; RV64I-MEDIUM-NEXT: .Lpcrel_hi6:
; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_4)
-; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB6_1)
+; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi6)
; RV64I-MEDIUM-NEXT: sd zero, 0(a0)
; RV64I-MEDIUM-NEXT: ret
entry:
@@ -295,10 +281,9 @@ define dso_local void @store_g_8() nounwind {
;
; RV32I-MEDIUM-LABEL: store_g_8:
; RV32I-MEDIUM: # %bb.0: # %entry
-; RV32I-MEDIUM-NEXT: .LBB7_1: # %entry
-; RV32I-MEDIUM-NEXT: # Label of block must be emitted
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi7:
; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_8)
-; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB7_1)
+; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi7)
; RV32I-MEDIUM-NEXT: sw zero, 4(a0)
; RV32I-MEDIUM-NEXT: sw zero, 0(a0)
; RV32I-MEDIUM-NEXT: ret
@@ -311,10 +296,9 @@ define dso_local void @store_g_8() nounwind {
;
; RV64I-MEDIUM-LABEL: store_g_8:
; RV64I-MEDIUM: # %bb.0: # %entry
-; RV64I-MEDIUM-NEXT: .LBB7_1: # %entry
-; RV64I-MEDIUM-NEXT: # Label of block must be emitted
+; RV64I-MEDIUM-NEXT: .Lpcrel_hi7:
; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_8)
-; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB7_1)
+; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi7)
; RV64I-MEDIUM-NEXT: sd zero, 0(a0)
; RV64I-MEDIUM-NEXT: ret
entry:
@@ -338,10 +322,9 @@ define dso_local void @inc_g_i32() nounwind {
;
; RV32I-MEDIUM-LABEL: inc_g_i32:
; RV32I-MEDIUM: # %bb.0: # %entry
-; RV32I-MEDIUM-NEXT: .LBB8_1: # %entry
-; RV32I-MEDIUM-NEXT: # Label of block must be emitted
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi8:
; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_4_i32)
-; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB8_1)
+; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi8)
; RV32I-MEDIUM-NEXT: lw a1, 0(a0)
; RV32I-MEDIUM-NEXT: addi a1, a1, 1
; RV32I-MEDIUM-NEXT: sw a1, 0(a0)
@@ -357,10 +340,9 @@ define dso_local void @inc_g_i32() nounwind {
;
; RV64I-MEDIUM-LABEL: inc_g_i32:
; RV64I-MEDIUM: # %bb.0: # %entry
-; RV64I-MEDIUM-NEXT: .LBB8_1: # %entry
-; RV64I-MEDIUM-NEXT: # Label of block must be emitted
+; RV64I-MEDIUM-NEXT: .Lpcrel_hi8:
; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_4_i32)
-; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB8_1)
+; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi8)
; RV64I-MEDIUM-NEXT: lw a1, 0(a0)
; RV64I-MEDIUM-NEXT: addiw a1, a1, 1
; RV64I-MEDIUM-NEXT: sw a1, 0(a0)
@@ -388,9 +370,9 @@ define dso_local i32 @load_ga() local_unnamed_addr #0 {
;
; RV32I-MEDIUM-LABEL: load_ga:
; RV32I-MEDIUM: # %bb.0:
-; RV32I-MEDIUM-NEXT: .LBB9_1: # Label of block must be emitted
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi9:
; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(ga)
-; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB9_1)
+; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi9)
; RV32I-MEDIUM-NEXT: lw a0, 4(a0)
; RV32I-MEDIUM-NEXT: ret
;
@@ -402,9 +384,9 @@ define dso_local i32 @load_ga() local_unnamed_addr #0 {
;
; RV64I-MEDIUM-LABEL: load_ga:
; RV64I-MEDIUM: # %bb.0:
-; RV64I-MEDIUM-NEXT: .LBB9_1: # Label of block must be emitted
+; RV64I-MEDIUM-NEXT: .Lpcrel_hi9:
; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(ga)
-; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB9_1)
+; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi9)
; RV64I-MEDIUM-NEXT: lw a0, 4(a0)
; RV64I-MEDIUM-NEXT: ret
%1 = load i32, i32* getelementptr inbounds ([2 x i32], [2 x i32]* @ga, i32 0, i32 1), align 4
@@ -427,10 +409,9 @@ define dso_local i64 @load_ga_8() nounwind {
;
; RV32I-MEDIUM-LABEL: load_ga_8:
; RV32I-MEDIUM: # %bb.0: # %entry
-; RV32I-MEDIUM-NEXT: .LBB10_1: # %entry
-; RV32I-MEDIUM-NEXT: # Label of block must be emitted
-; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(ga_8)
-; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB10_1)
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi10:
+; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(ga_8)
+; RV32I-MEDIUM-NEXT: addi a1, a0, %pcrel_lo(.Lpcrel_hi10)
; RV32I-MEDIUM-NEXT: lw a0, 8(a1)
; RV32I-MEDIUM-NEXT: lw a1, 12(a1)
; RV32I-MEDIUM-NEXT: ret
@@ -443,10 +424,9 @@ define dso_local i64 @load_ga_8() nounwind {
;
; RV64I-MEDIUM-LABEL: load_ga_8:
; RV64I-MEDIUM: # %bb.0: # %entry
-; RV64I-MEDIUM-NEXT: .LBB10_1: # %entry
-; RV64I-MEDIUM-NEXT: # Label of block must be emitted
+; RV64I-MEDIUM-NEXT: .Lpcrel_hi10:
; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(ga_8)
-; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB10_1)
+; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi10)
; RV64I-MEDIUM-NEXT: ld a0, 8(a0)
; RV64I-MEDIUM-NEXT: ret
entry:
@@ -464,10 +444,9 @@ define dso_local i64 @load_ga_16() nounwind {
;
; RV32I-MEDIUM-LABEL: load_ga_16:
; RV32I-MEDIUM: # %bb.0: # %entry
-; RV32I-MEDIUM-NEXT: .LBB11_1: # %entry
-; RV32I-MEDIUM-NEXT: # Label of block must be emitted
-; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(ga_16)
-; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB11_1)
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi11:
+; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(ga_16)
+; RV32I-MEDIUM-NEXT: addi a1, a0, %pcrel_lo(.Lpcrel_hi11)
; RV32I-MEDIUM-NEXT: lw a0, 8(a1)
; RV32I-MEDIUM-NEXT: lw a1, 12(a1)
; RV32I-MEDIUM-NEXT: ret
@@ -480,10 +459,9 @@ define dso_local i64 @load_ga_16() nounwind {
;
; RV64I-MEDIUM-LABEL: load_ga_16:
; RV64I-MEDIUM: # %bb.0: # %entry
-; RV64I-MEDIUM-NEXT: .LBB11_1: # %entry
-; RV64I-MEDIUM-NEXT: # Label of block must be emitted
+; RV64I-MEDIUM-NEXT: .Lpcrel_hi11:
; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(ga_16)
-; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.LBB11_1)
+; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi11)
; RV64I-MEDIUM-NEXT: ld a0, 8(a0)
; RV64I-MEDIUM-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/jumptable.ll b/llvm/test/CodeGen/RISCV/jumptable.ll
index ab638aaefeadc..86a1273190d13 100644
--- a/llvm/test/CodeGen/RISCV/jumptable.ll
+++ b/llvm/test/CodeGen/RISCV/jumptable.ll
@@ -203,10 +203,9 @@ define void @above_threshold(i32 %in, i32* %out) nounwind {
; RV32I-MEDIUM-NEXT: bltu a2, a0, .LBB1_9
; RV32I-MEDIUM-NEXT: # %bb.1: # %entry
; RV32I-MEDIUM-NEXT: slli a0, a0, 2
-; RV32I-MEDIUM-NEXT: .LBB1_10: # %entry
-; RV32I-MEDIUM-NEXT: # Label of block must be emitted
+; RV32I-MEDIUM-NEXT: .Lpcrel_hi0:
; RV32I-MEDIUM-NEXT: auipc a2, %pcrel_hi(.LJTI1_0)
-; RV32I-MEDIUM-NEXT: addi a2, a2, %pcrel_lo(.LBB1_10)
+; RV32I-MEDIUM-NEXT: addi a2, a2, %pcrel_lo(.Lpcrel_hi0)
; RV32I-MEDIUM-NEXT: add a0, a0, a2
; RV32I-MEDIUM-NEXT: lw a0, 0(a0)
; RV32I-MEDIUM-NEXT: jr a0
@@ -275,10 +274,9 @@ define void @above_threshold(i32 %in, i32* %out) nounwind {
; RV64I-MEDIUM-NEXT: bltu a2, a0, .LBB1_9
; RV64I-MEDIUM-NEXT: # %bb.1: # %entry
; RV64I-MEDIUM-NEXT: slli a0, a0, 3
-; RV64I-MEDIUM-NEXT: .LBB1_10: # %entry
-; RV64I-MEDIUM-NEXT: # Label of block must be emitted
+; RV64I-MEDIUM-NEXT: .Lpcrel_hi0:
; RV64I-MEDIUM-NEXT: auipc a2, %pcrel_hi(.LJTI1_0)
-; RV64I-MEDIUM-NEXT: addi a2, a2, %pcrel_lo(.LBB1_10)
+; RV64I-MEDIUM-NEXT: addi a2, a2, %pcrel_lo(.Lpcrel_hi0)
; RV64I-MEDIUM-NEXT: add a0, a0, a2
; RV64I-MEDIUM-NEXT: ld a0, 0(a0)
; RV64I-MEDIUM-NEXT: jr a0
diff --git a/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll b/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
index ae4697b43fbf4..cb7325dcbc431 100644
--- a/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
+++ b/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
@@ -12,10 +12,9 @@ define void @test_lla(i32 signext %n) {
; RV32I-LABEL: test_lla:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 0
-; RV32I-NEXT: .LBB0_3: # %entry
-; RV32I-NEXT: # Label of block must be emitted
+; RV32I-NEXT: .Lpcrel_hi0:
; RV32I-NEXT: auipc a2, %pcrel_hi(l)
-; RV32I-NEXT: addi a2, a2, %pcrel_lo(.LBB0_3)
+; RV32I-NEXT: addi a2, a2, %pcrel_lo(.Lpcrel_hi0)
; RV32I-NEXT: .LBB0_1: # %loop
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: lw a3, 0(a2)
@@ -27,10 +26,9 @@ define void @test_lla(i32 signext %n) {
; RV64I-LABEL: test_lla:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: li a1, 0
-; RV64I-NEXT: .LBB0_3: # %entry
-; RV64I-NEXT: # Label of block must be emitted
+; RV64I-NEXT: .Lpcrel_hi0:
; RV64I-NEXT: auipc a2, %pcrel_hi(l)
-; RV64I-NEXT: addi a2, a2, %pcrel_lo(.LBB0_3)
+; RV64I-NEXT: addi a2, a2, %pcrel_lo(.Lpcrel_hi0)
; RV64I-NEXT: .LBB0_1: # %loop
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: lw a3, 0(a2)
@@ -57,10 +55,9 @@ ret:
define void @test_la(i32 signext %n) {
; RV32I-LABEL: test_la:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: .LBB1_3: # %entry
-; RV32I-NEXT: # Label of block must be emitted
+; RV32I-NEXT: .Lpcrel_hi1:
; RV32I-NEXT: auipc a1, %got_pcrel_hi(g)
-; RV32I-NEXT: lw a1, %pcrel_lo(.LBB1_3)(a1)
+; RV32I-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi1)(a1)
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: .LBB1_1: # %loop
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -72,10 +69,9 @@ define void @test_la(i32 signext %n) {
;
; RV64I-LABEL: test_la:
; RV64I: # %bb.0: # %entry
-; RV64I-NEXT: .LBB1_3: # %entry
-; RV64I-NEXT: # Label of block must be emitted
+; RV64I-NEXT: .Lpcrel_hi1:
; RV64I-NEXT: auipc a1, %got_pcrel_hi(g)
-; RV64I-NEXT: ld a1, %pcrel_lo(.LBB1_3)(a1)
+; RV64I-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi1)(a1)
; RV64I-NEXT: li a2, 0
; RV64I-NEXT: .LBB1_1: # %loop
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -103,10 +99,9 @@ ret:
define void @test_la_tls_ie(i32 signext %n) {
; RV32I-LABEL: test_la_tls_ie:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: .LBB2_3: # %entry
-; RV32I-NEXT: # Label of block must be emitted
-; RV32I-NEXT: auipc a2, %tls_ie_pcrel_hi(ie)
-; RV32I-NEXT: lw a2, %pcrel_lo(.LBB2_3)(a2)
+; RV32I-NEXT: .Lpcrel_hi2:
+; RV32I-NEXT: auipc a1, %tls_ie_pcrel_hi(ie)
+; RV32I-NEXT: lw a2, %pcrel_lo(.Lpcrel_hi2)(a1)
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: add a2, a2, tp
; RV32I-NEXT: .LBB2_1: # %loop
@@ -119,10 +114,9 @@ define void @test_la_tls_ie(i32 signext %n) {
;
; RV64I-LABEL: test_la_tls_ie:
; RV64I: # %bb.0: # %entry
-; RV64I-NEXT: .LBB2_3: # %entry
-; RV64I-NEXT: # Label of block must be emitted
-; RV64I-NEXT: auipc a2, %tls_ie_pcrel_hi(ie)
-; RV64I-NEXT: ld a2, %pcrel_lo(.LBB2_3)(a2)
+; RV64I-NEXT: .Lpcrel_hi2:
+; RV64I-NEXT: auipc a1, %tls_ie_pcrel_hi(ie)
+; RV64I-NEXT: ld a2, %pcrel_lo(.Lpcrel_hi2)(a1)
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: add a2, a2, tp
; RV64I-NEXT: .LBB2_1: # %loop
@@ -158,10 +152,9 @@ define void @test_la_tls_gd(i32 signext %n) nounwind {
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li s2, 0
-; RV32I-NEXT: .LBB3_3: # %entry
-; RV32I-NEXT: # Label of block must be emitted
-; RV32I-NEXT: auipc s1, %tls_gd_pcrel_hi(gd)
-; RV32I-NEXT: addi s1, s1, %pcrel_lo(.LBB3_3)
+; RV32I-NEXT: .Lpcrel_hi3:
+; RV32I-NEXT: auipc a0, %tls_gd_pcrel_hi(gd)
+; RV32I-NEXT: addi s1, a0, %pcrel_lo(.Lpcrel_hi3)
; RV32I-NEXT: .LBB3_1: # %loop
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1
@@ -186,10 +179,9 @@ define void @test_la_tls_gd(i32 signext %n) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li s2, 0
-; RV64I-NEXT: .LBB3_3: # %entry
-; RV64I-NEXT: # Label of block must be emitted
-; RV64I-NEXT: auipc s1, %tls_gd_pcrel_hi(gd)
-; RV64I-NEXT: addi s1, s1, %pcrel_lo(.LBB3_3)
+; RV64I-NEXT: .Lpcrel_hi3:
+; RV64I-NEXT: auipc a0, %tls_gd_pcrel_hi(gd)
+; RV64I-NEXT: addi s1, a0, %pcrel_lo(.Lpcrel_hi3)
; RV64I-NEXT: .LBB3_1: # %loop
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1
diff --git a/llvm/test/CodeGen/RISCV/mir-target-flags.ll b/llvm/test/CodeGen/RISCV/mir-target-flags.ll
index 5cdebf1ef2d21..810667243fdcc 100644
--- a/llvm/test/CodeGen/RISCV/mir-target-flags.ll
+++ b/llvm/test/CodeGen/RISCV/mir-target-flags.ll
@@ -1,11 +1,11 @@
; RUN: llc -mtriple=riscv32 --code-model=small \
-; RUN: -stop-after riscv-expand-pseudo %s -o %t.mir
-; RUN: llc -mtriple=riscv32 -run-pass none %t.mir -o - | \
+; RUN: -stop-after riscv-prera-expand-pseudo %s -o %t.mir
+; RUN: llc -mtriple=riscv32 -run-pass riscv-expand-pseudo %t.mir -o - | \
; RUN: FileCheck %s -check-prefix=RV32-SMALL
;
; RUN: llc -mtriple=riscv32 --code-model=medium --relocation-model=pic \
-; RUN: -stop-after riscv-expand-pseudo %s -o %t.mir
-; RUN: llc -mtriple=riscv32 -run-pass none %t.mir -o - | \
+; RUN: -stop-after riscv-prera-expand-pseudo %s -o %t.mir
+; RUN: llc -mtriple=riscv32 -run-pass riscv-expand-pseudo %t.mir -o - | \
; RUN: FileCheck %s -check-prefix=RV32-MED
; This tests the RISC-V-specific serialization and deserialization of
@@ -24,14 +24,14 @@ define i32 @caller(i32 %a) nounwind {
; RV32-SMALL-LABEL: name: caller
; RV32-SMALL: target-flags(riscv-hi) @g_e
; RV32-SMALL-NEXT: target-flags(riscv-lo) @g_e
-; RV32-SMALL: target-flags(riscv-tls-got-hi) @t_un
-; RV32-SMALL-NEXT: target-flags(riscv-pcrel-lo) %bb.1
; RV32-SMALL: target-flags(riscv-hi) @g_i
; RV32-SMALL-NEXT: target-flags(riscv-lo) @g_i
+; RV32-SMALL: target-flags(riscv-tls-got-hi) @t_un
+; RV32-SMALL-NEXT: target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi0>
; RV32-SMALL: target-flags(riscv-tls-got-hi) @t_ld
-; RV32-SMALL-NEXT: target-flags(riscv-pcrel-lo) %bb.2
+; RV32-SMALL-NEXT: target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1>
; RV32-SMALL: target-flags(riscv-tls-got-hi) @t_ie
-; RV32-SMALL-NEXT: target-flags(riscv-pcrel-lo) %bb.3
+; RV32-SMALL-NEXT: target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi2>
; RV32-SMALL: target-flags(riscv-tprel-hi) @t_le
; RV32-SMALL-NEXT: target-flags(riscv-tprel-add) @t_le
; RV32-SMALL-NEXT: target-flags(riscv-tprel-lo) @t_le
@@ -39,17 +39,17 @@ define i32 @caller(i32 %a) nounwind {
;
; RV32-MED-LABEL: name: caller
; RV32-MED: target-flags(riscv-got-hi) @g_e
-; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.1
+; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi0>
; RV32-MED: target-flags(riscv-pcrel-hi) @g_i
-; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.2
+; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1>
; RV32-MED: target-flags(riscv-tls-gd-hi) @t_un
-; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.3
-; RV32-MED-NEXT: target-flags(riscv-plt) &__tls_get_addr
+; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi2>
+; RV32-MED: target-flags(riscv-plt) &__tls_get_addr
; RV32-MED: target-flags(riscv-tls-gd-hi) @t_ld
-; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.4
-; RV32-MED-NEXT: target-flags(riscv-plt) &__tls_get_addr
+; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi3>
+; RV32-MED: target-flags(riscv-plt) &__tls_get_addr
; RV32-MED: target-flags(riscv-tls-got-hi) @t_ie
-; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.5
+; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi4>
; RV32-MED: target-flags(riscv-tprel-hi) @t_le
; RV32-MED-NEXT: target-flags(riscv-tprel-add) @t_le
; RV32-MED-NEXT: target-flags(riscv-tprel-lo) @t_le
diff --git a/llvm/test/CodeGen/RISCV/pic-models.ll b/llvm/test/CodeGen/RISCV/pic-models.ll
index 8d835ae99f406..0b12aee16c384 100644
--- a/llvm/test/CodeGen/RISCV/pic-models.ll
+++ b/llvm/test/CodeGen/RISCV/pic-models.ll
@@ -26,10 +26,9 @@ define i32* @f1() nounwind {
;
; RV32-PIC-LABEL: f1:
; RV32-PIC: # %bb.0: # %entry
-; RV32-PIC-NEXT: .LBB0_1: # %entry
-; RV32-PIC-NEXT: # Label of block must be emitted
+; RV32-PIC-NEXT: .Lpcrel_hi0:
; RV32-PIC-NEXT: auipc a0, %got_pcrel_hi(external_var)
-; RV32-PIC-NEXT: lw a0, %pcrel_lo(.LBB0_1)(a0)
+; RV32-PIC-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi0)(a0)
; RV32-PIC-NEXT: ret
;
; RV64-STATIC-LABEL: f1:
@@ -40,10 +39,9 @@ define i32* @f1() nounwind {
;
; RV64-PIC-LABEL: f1:
; RV64-PIC: # %bb.0: # %entry
-; RV64-PIC-NEXT: .LBB0_1: # %entry
-; RV64-PIC-NEXT: # Label of block must be emitted
+; RV64-PIC-NEXT: .Lpcrel_hi0:
; RV64-PIC-NEXT: auipc a0, %got_pcrel_hi(external_var)
-; RV64-PIC-NEXT: ld a0, %pcrel_lo(.LBB0_1)(a0)
+; RV64-PIC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi0)(a0)
; RV64-PIC-NEXT: ret
entry:
ret i32* @external_var
@@ -61,10 +59,9 @@ define i32* @f2() nounwind {
;
; RV32-PIC-LABEL: f2:
; RV32-PIC: # %bb.0: # %entry
-; RV32-PIC-NEXT: .LBB1_1: # %entry
-; RV32-PIC-NEXT: # Label of block must be emitted
+; RV32-PIC-NEXT: .Lpcrel_hi1:
; RV32-PIC-NEXT: auipc a0, %pcrel_hi(internal_var)
-; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB1_1)
+; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi1)
; RV32-PIC-NEXT: ret
;
; RV64-STATIC-LABEL: f2:
@@ -75,10 +72,9 @@ define i32* @f2() nounwind {
;
; RV64-PIC-LABEL: f2:
; RV64-PIC: # %bb.0: # %entry
-; RV64-PIC-NEXT: .LBB1_1: # %entry
-; RV64-PIC-NEXT: # Label of block must be emitted
+; RV64-PIC-NEXT: .Lpcrel_hi1:
; RV64-PIC-NEXT: auipc a0, %pcrel_hi(internal_var)
-; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB1_1)
+; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi1)
; RV64-PIC-NEXT: ret
entry:
ret i32* @internal_var
diff --git a/llvm/test/CodeGen/RISCV/tls-models.ll b/llvm/test/CodeGen/RISCV/tls-models.ll
index e3836eefad7c5..bd5fee639a47e 100644
--- a/llvm/test/CodeGen/RISCV/tls-models.ll
+++ b/llvm/test/CodeGen/RISCV/tls-models.ll
@@ -23,10 +23,9 @@ define i32* @f1() nounwind {
; RV32-PIC: # %bb.0: # %entry
; RV32-PIC-NEXT: addi sp, sp, -16
; RV32-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-PIC-NEXT: .LBB0_1: # %entry
-; RV32-PIC-NEXT: # Label of block must be emitted
+; RV32-PIC-NEXT: .Lpcrel_hi0:
; RV32-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(unspecified)
-; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB0_1)
+; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi0)
; RV32-PIC-NEXT: call __tls_get_addr at plt
; RV32-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-PIC-NEXT: addi sp, sp, 16
@@ -36,10 +35,9 @@ define i32* @f1() nounwind {
; RV64-PIC: # %bb.0: # %entry
; RV64-PIC-NEXT: addi sp, sp, -16
; RV64-PIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-PIC-NEXT: .LBB0_1: # %entry
-; RV64-PIC-NEXT: # Label of block must be emitted
+; RV64-PIC-NEXT: .Lpcrel_hi0:
; RV64-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(unspecified)
-; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB0_1)
+; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi0)
; RV64-PIC-NEXT: call __tls_get_addr at plt
; RV64-PIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-PIC-NEXT: addi sp, sp, 16
@@ -47,19 +45,17 @@ define i32* @f1() nounwind {
;
; RV32-NOPIC-LABEL: f1:
; RV32-NOPIC: # %bb.0: # %entry
-; RV32-NOPIC-NEXT: .LBB0_1: # %entry
-; RV32-NOPIC-NEXT: # Label of block must be emitted
+; RV32-NOPIC-NEXT: .Lpcrel_hi0:
; RV32-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(unspecified)
-; RV32-NOPIC-NEXT: lw a0, %pcrel_lo(.LBB0_1)(a0)
+; RV32-NOPIC-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi0)(a0)
; RV32-NOPIC-NEXT: add a0, a0, tp
; RV32-NOPIC-NEXT: ret
;
; RV64-NOPIC-LABEL: f1:
; RV64-NOPIC: # %bb.0: # %entry
-; RV64-NOPIC-NEXT: .LBB0_1: # %entry
-; RV64-NOPIC-NEXT: # Label of block must be emitted
+; RV64-NOPIC-NEXT: .Lpcrel_hi0:
; RV64-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(unspecified)
-; RV64-NOPIC-NEXT: ld a0, %pcrel_lo(.LBB0_1)(a0)
+; RV64-NOPIC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi0)(a0)
; RV64-NOPIC-NEXT: add a0, a0, tp
; RV64-NOPIC-NEXT: ret
entry:
@@ -74,10 +70,9 @@ define i32* @f2() nounwind {
; RV32-PIC: # %bb.0: # %entry
; RV32-PIC-NEXT: addi sp, sp, -16
; RV32-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-PIC-NEXT: .LBB1_1: # %entry
-; RV32-PIC-NEXT: # Label of block must be emitted
+; RV32-PIC-NEXT: .Lpcrel_hi1:
; RV32-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(ld)
-; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB1_1)
+; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi1)
; RV32-PIC-NEXT: call __tls_get_addr at plt
; RV32-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-PIC-NEXT: addi sp, sp, 16
@@ -87,10 +82,9 @@ define i32* @f2() nounwind {
; RV64-PIC: # %bb.0: # %entry
; RV64-PIC-NEXT: addi sp, sp, -16
; RV64-PIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-PIC-NEXT: .LBB1_1: # %entry
-; RV64-PIC-NEXT: # Label of block must be emitted
+; RV64-PIC-NEXT: .Lpcrel_hi1:
; RV64-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(ld)
-; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB1_1)
+; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi1)
; RV64-PIC-NEXT: call __tls_get_addr at plt
; RV64-PIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-PIC-NEXT: addi sp, sp, 16
@@ -98,19 +92,17 @@ define i32* @f2() nounwind {
;
; RV32-NOPIC-LABEL: f2:
; RV32-NOPIC: # %bb.0: # %entry
-; RV32-NOPIC-NEXT: .LBB1_1: # %entry
-; RV32-NOPIC-NEXT: # Label of block must be emitted
+; RV32-NOPIC-NEXT: .Lpcrel_hi1:
; RV32-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(ld)
-; RV32-NOPIC-NEXT: lw a0, %pcrel_lo(.LBB1_1)(a0)
+; RV32-NOPIC-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi1)(a0)
; RV32-NOPIC-NEXT: add a0, a0, tp
; RV32-NOPIC-NEXT: ret
;
; RV64-NOPIC-LABEL: f2:
; RV64-NOPIC: # %bb.0: # %entry
-; RV64-NOPIC-NEXT: .LBB1_1: # %entry
-; RV64-NOPIC-NEXT: # Label of block must be emitted
+; RV64-NOPIC-NEXT: .Lpcrel_hi1:
; RV64-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(ld)
-; RV64-NOPIC-NEXT: ld a0, %pcrel_lo(.LBB1_1)(a0)
+; RV64-NOPIC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi1)(a0)
; RV64-NOPIC-NEXT: add a0, a0, tp
; RV64-NOPIC-NEXT: ret
entry:
@@ -123,37 +115,33 @@ entry:
define i32* @f3() nounwind {
; RV32-PIC-LABEL: f3:
; RV32-PIC: # %bb.0: # %entry
-; RV32-PIC-NEXT: .LBB2_1: # %entry
-; RV32-PIC-NEXT: # Label of block must be emitted
+; RV32-PIC-NEXT: .Lpcrel_hi2:
; RV32-PIC-NEXT: auipc a0, %tls_ie_pcrel_hi(ie)
-; RV32-PIC-NEXT: lw a0, %pcrel_lo(.LBB2_1)(a0)
+; RV32-PIC-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi2)(a0)
; RV32-PIC-NEXT: add a0, a0, tp
; RV32-PIC-NEXT: ret
;
; RV64-PIC-LABEL: f3:
; RV64-PIC: # %bb.0: # %entry
-; RV64-PIC-NEXT: .LBB2_1: # %entry
-; RV64-PIC-NEXT: # Label of block must be emitted
+; RV64-PIC-NEXT: .Lpcrel_hi2:
; RV64-PIC-NEXT: auipc a0, %tls_ie_pcrel_hi(ie)
-; RV64-PIC-NEXT: ld a0, %pcrel_lo(.LBB2_1)(a0)
+; RV64-PIC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi2)(a0)
; RV64-PIC-NEXT: add a0, a0, tp
; RV64-PIC-NEXT: ret
;
; RV32-NOPIC-LABEL: f3:
; RV32-NOPIC: # %bb.0: # %entry
-; RV32-NOPIC-NEXT: .LBB2_1: # %entry
-; RV32-NOPIC-NEXT: # Label of block must be emitted
+; RV32-NOPIC-NEXT: .Lpcrel_hi2:
; RV32-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(ie)
-; RV32-NOPIC-NEXT: lw a0, %pcrel_lo(.LBB2_1)(a0)
+; RV32-NOPIC-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi2)(a0)
; RV32-NOPIC-NEXT: add a0, a0, tp
; RV32-NOPIC-NEXT: ret
;
; RV64-NOPIC-LABEL: f3:
; RV64-NOPIC: # %bb.0: # %entry
-; RV64-NOPIC-NEXT: .LBB2_1: # %entry
-; RV64-NOPIC-NEXT: # Label of block must be emitted
+; RV64-NOPIC-NEXT: .Lpcrel_hi2:
; RV64-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(ie)
-; RV64-NOPIC-NEXT: ld a0, %pcrel_lo(.LBB2_1)(a0)
+; RV64-NOPIC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi2)(a0)
; RV64-NOPIC-NEXT: add a0, a0, tp
; RV64-NOPIC-NEXT: ret
entry:
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