[llvm] a14f94c - [X86] computeKnownBitsForTargetNode - out of range X86ISD::VSRAI doesn't fold to zero

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-07-30T17:55:39+01:00
New Revision: a14f94c20c65c80ba712567c4e8cb55dd939415b

URL: https://github.com/llvm/llvm-project/commit/a14f94c20c65c80ba712567c4e8cb55dd939415b
DIFF: https://github.com/llvm/llvm-project/commit/a14f94c20c65c80ba712567c4e8cb55dd939415b.diff

LOG: [X86] computeKnownBitsForTargetNode - out of range X86ISD::VSRAI doesn't fold to zero

Noticed by inspection and I can't seem to make a test case, but SSE arithmetic bit shifts clamp to the max shift amount (i.e. create a sign splat) - combineVectorShiftImm already does something similar.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a53995e6df7fc..9f2385c6eebbf 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -36720,8 +36720,14 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
   case X86ISD::VSRLI: {
     unsigned ShAmt = Op.getConstantOperandVal(1);
     if (ShAmt >= VT.getScalarSizeInBits()) {
-      Known.setAllZero();
-      break;
+      // Out of range logical bit shifts are guaranteed to be zero.
+      // Out of range arithmetic bit shifts splat the sign bit.
+      if (Opc != X86ISD::VSRAI) {
+        Known.setAllZero();
+        break;
+      }
+
+      ShAmt = VT.getScalarSizeInBits() - 1;
     }
 
     Known = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);