[PATCH] D130816: [RISCV] Add merge operands to more RISCVISD::*_VL opcodes.

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM.  Idea makes sense, optional comments.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:216
 
-  // Vector binary and unary ops with a mask as a third operand, and VL as a
-  // fourth operand.
+  // Vector binary ops with a mask as a third operand, a merge value
+  // as a fourth operand, and VL as a fifth operand.
----------------
This is a purely stylistic comment - but I find the placement of merge between mask and VL slightly surprising.  Would it be easy to make the order merge, mask, VL?  This would keep this matching the MI operand order as much as possible while still obeying the commutative restriction to not have merge first in the sequence.  


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:251
+
+  // Vector FMA ops with a mask as a second operand and VL as a third operand.
   FNEG_VL,
----------------
I think you meant unary not FMA here right?


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  https://reviews.llvm.org/D130816/new/

https://reviews.llvm.org/D130816