[PATCH] D130764: [AMDGPU] Enable image_gather4h instruction for gfx10 and gfx11

Fri Jul 29 06:44:29 PDT 2022

This revision was automatically updated to reflect the committed changes.
Closed by commit rG6a1aa627faa2: [AMDGPU] Enable image_gather4h instruction for gfx10 and gfx11 (authored by mbrkusanin).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130764/new/

https://reviews.llvm.org/D130764

Files:
  llvm/lib/Target/AMDGPU/MIMGInstructions.td
  llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
  llvm/test/MC/AMDGPU/gfx11_asm_mimg.s
  llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
  llvm/test/MC/Disassembler/AMDGPU/gfx11_mimg.txt


Index: llvm/test/MC/Disassembler/AMDGPU/gfx11_mimg.txt
===================================================================

--- llvm/test/MC/Disassembler/AMDGPU/gfx11_mimg.txt
+++ llvm/test/MC/Disassembler/AMDGPU/gfx11_mimg.txt
@@ -258,6 +258,9 @@
 # GFX11: image_gather4_c_lz_o v[64:67], [v32, v0, v4, v5, v6], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x09,0x01,0xdc,0xf0,0x20,0x40,0x01,0x64,0x00,0x04,0x05,0x06]
 0x09,0x01,0xdc,0xf0,0x20,0x40,0x01,0x64,0x00,0x04,0x05,0x06
 
+# GFX11: image_gather4h v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x0d,0x02,0x40,0xf2,0x20,0x40,0x01,0x04,0x21,0x22,0x00,0x00]
+0x0d,0x02,0x40,0xf2,0x20,0x40,0x01,0x04,0x21,0x22,0x00,0x00
+
 # GFX11: image_get_lod v64, v[32:33], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x04,0x01,0xe0,0xf0,0x20,0x40,0x01,0x64]
 0x04,0x01,0xe0,0xf0,0x20,0x40,0x01,0x64
 
Index: llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
===================================================================
--- llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
+++ llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
@@ -512,6 +512,9 @@
 # GFX10: image_gather4_c_lz_o v[16:19], [v8, v9, v10, v11], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0a,0x0f,0x7c,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x00]
 0x0a,0x0f,0x7c,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
 
+# GFX10: image_gather4h v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x1a,0x02,0x84,0xf1,0x20,0x40,0x21,0x00,0x21,0x22,0x00,0x00]
+0x1a,0x02,0x84,0xf1,0x20,0x40,0x21,0x00,0x21,0x22,0x00,0x00
+
 # GFX10: image_get_lod v[16:19], [v8, v9, v10], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x12,0x0f,0x80,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00]
 0x12,0x0f,0x80,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
 
Index: llvm/test/MC/AMDGPU/gfx11_asm_mimg.s
===================================================================
--- llvm/test/MC/AMDGPU/gfx11_asm_mimg.s
+++ llvm/test/MC/AMDGPU/gfx11_asm_mimg.s
@@ -259,6 +259,9 @@
 image_gather4_c_lz_o v[64:67], [v32, v0, v4, v5, v6], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_3D
 ; GFX11: image_gather4_c_lz_o v[64:67], [v32, v0, v4, v5, v6], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x09,0x01,0xdc,0xf0,0x20,0x40,0x01,0x64,0x00,0x04,0x05,0x06]
 
+image_gather4h v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+; GFX11: image_gather4h v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x0d,0x02,0x40,0xf2,0x20,0x40,0x01,0x04,0x21,0x22,0x00,0x00]
+
 image_get_lod v64, v[32:33], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_2D
 ; GFX11: image_get_lod v64, v[32:33], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x04,0x01,0xe0,0xf0,0x20,0x40,0x01,0x64]
 
Index: llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
===================================================================
--- llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
+++ llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
@@ -469,6 +469,9 @@
 image_gather4_c_lz_o v[64:67], [v32, v0, v4, v5, v6], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_3D
 ; GFX10: image_gather4_c_lz_o v[64:67], [v32, v0, v4, v5, v6], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x12,0x01,0x7c,0xf1,0x20,0x40,0x21,0x03,0x00,0x04,0x05,0x06]
 
+image_gather4h v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
+; GFX10: image_gather4h v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x1a,0x02,0x84,0xf1,0x20,0x40,0x21,0x00,0x21,0x22,0x00,0x00]
+
 image_get_lod v64, v[32:33], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_2D
 ; GFX10: image_get_lod v64, v[32:33], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x01,0x80,0xf1,0x20,0x40,0x21,0x03]
 
Index: llvm/lib/Target/AMDGPU/MIMGInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -1325,7 +1325,7 @@
 defm IMAGE_GATHER4_C_B_O        : MIMG_Gather_WQM <mimgopc<MIMG.NOP, 0x5d>, AMDGPUSample_c_b_o>;
 defm IMAGE_GATHER4_C_B_CL_O     : MIMG_Gather_WQM <mimgopc<MIMG.NOP, 0x5e>, AMDGPUSample_c_b_cl_o>;
 defm IMAGE_GATHER4_C_LZ_O       : MIMG_Gather <mimgopc<0x37, 0x5f>, AMDGPUSample_c_lz_o>;
-//defm IMAGE_GATHER4H             : MIMG_Gather_WQM <mimgopc<0x90, 0x61>, ?>;
+defm IMAGE_GATHER4H             : MIMG_Gather <mimgopc<0x90, 0x61>, AMDGPUSample, 1, "image_gather4h">;
 
 defm IMAGE_GET_LOD              : MIMG_Sampler <mimgopc<0x38, 0x60>, AMDGPUSample, 1, 0, 1, "image_get_lod">;
 


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