[llvm] 56ab2f4 - [LoongArch] Offset folding for frameindex
Weining Lu via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 29 02:28:09 PDT 2022
Author: wanglei
Date: 2022-07-29T17:27:34+08:00
New Revision: 56ab2f4ccd30f1815929e207334511316218a838
URL: https://github.com/llvm/llvm-project/commit/56ab2f4ccd30f1815929e207334511316218a838
DIFF: https://github.com/llvm/llvm-project/commit/56ab2f4ccd30f1815929e207334511316218a838.diff
LOG: [LoongArch] Offset folding for frameindex
This patch is for frameindex calculations.
Differential Revision: https://reviews.llvm.org/D130248
Added:
Modified:
llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
llvm/test/CodeGen/LoongArch/frame.ll
llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll
llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
index d07d086bd7da..faffe95c1e77 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -587,6 +587,12 @@ class PatGprImm_32<SDPatternOperator OpNode, LAInst Inst, Operand ImmOpnd>
: Pat<(sext_inreg (OpNode GPR:$rj, ImmOpnd:$imm), i32),
(Inst GPR:$rj, ImmOpnd:$imm)>;
+/// Predicates
+def AddLike: PatFrags<(ops node:$A, node:$B),
+ [(add node:$A, node:$B), (or node:$A, node:$B)], [{
+ return N->getOpcode() == ISD::ADD || isOrEquivalentToAdd(N);
+}]>;
+
/// Simple arithmetic operations
// Match both a plain shift and one where the shift amount is masked (this is
@@ -654,6 +660,16 @@ def : PatGprImm<or, ORI, uimm12>;
def : PatGprGpr<xor, XOR>;
def : PatGprImm<xor, XORI, uimm12>;
+/// FrameIndex calculations
+let Predicates = [IsLA32] in {
+def : Pat<(AddLike (i32 BaseAddr:$rj), simm12:$imm12),
+ (ADDI_W (i32 BaseAddr:$rj), simm12:$imm12)>;
+} // Predicates = [IsLA32]
+let Predicates = [IsLA64] in {
+def : Pat<(AddLike (i64 BaseAddr:$rj), simm12:$imm12),
+ (ADDI_D (i64 BaseAddr:$rj), simm12:$imm12)>;
+} // Predicates = [IsLA64]
+
/// Shift
let Predicates = [IsLA32] in {
@@ -804,7 +820,7 @@ def : Pat<(loongarch_bstrpick GPR:$rj, uimm6:$msbd, uimm6:$lsbd),
multiclass LdPat<PatFrag LoadOp, LAInst Inst, ValueType vt = GRLenVT> {
def : Pat<(vt (LoadOp BaseAddr:$rj)), (Inst BaseAddr:$rj, 0)>;
- def : Pat<(vt (LoadOp (add BaseAddr:$rj, simm12:$imm12))),
+ def : Pat<(vt (LoadOp (AddLike BaseAddr:$rj, simm12:$imm12))),
(Inst BaseAddr:$rj, simm12:$imm12)>;
}
@@ -828,7 +844,7 @@ multiclass StPat<PatFrag StoreOp, LAInst Inst, RegisterClass StTy,
ValueType vt> {
def : Pat<(StoreOp (vt StTy:$rd), BaseAddr:$rj),
(Inst StTy:$rd, BaseAddr:$rj, 0)>;
- def : Pat<(StoreOp (vt StTy:$rd), (add BaseAddr:$rj, simm12:$imm12)),
+ def : Pat<(StoreOp (vt StTy:$rd), (AddLike BaseAddr:$rj, simm12:$imm12)),
(Inst StTy:$rd, BaseAddr:$rj, simm12:$imm12)>;
}
diff --git a/llvm/test/CodeGen/LoongArch/frame.ll b/llvm/test/CodeGen/LoongArch/frame.ll
index e0aa7db13f72..04f59d282753 100644
--- a/llvm/test/CodeGen/LoongArch/frame.ll
+++ b/llvm/test/CodeGen/LoongArch/frame.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
%struct.key_t = type { i32, [16 x i8] }
@@ -10,8 +11,7 @@ define i32 @test() nounwind {
; CHECK-NEXT: st.w $zero, $sp, 16
; CHECK-NEXT: st.d $zero, $sp, 8
; CHECK-NEXT: st.d $zero, $sp, 0
-; CHECK-NEXT: addi.d $a0, $sp, 0
-; CHECK-NEXT: ori $a0, $a0, 4
+; CHECK-NEXT: addi.d $a0, $sp, 4
; CHECK-NEXT: bl test1
; CHECK-NEXT: move $a0, $zero
; CHECK-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll
index 33f6dbee748e..1be434ef182e 100644
--- a/llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll
+++ b/llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll
@@ -229,10 +229,8 @@ define double @convert_u32_to_double(i32 %a) nounwind {
; LA32-LABEL: convert_u32_to_double:
; LA32: # %bb.0:
; LA32-NEXT: addi.w $sp, $sp, -16
-; LA32-NEXT: addi.w $a1, $sp, 8
-; LA32-NEXT: ori $a1, $a1, 4
-; LA32-NEXT: lu12i.w $a2, 275200
-; LA32-NEXT: st.w $a2, $a1, 0
+; LA32-NEXT: lu12i.w $a1, 275200
+; LA32-NEXT: st.w $a1, $sp, 12
; LA32-NEXT: st.w $a0, $sp, 8
; LA32-NEXT: pcalau12i $a0, .LCPI12_0
; LA32-NEXT: addi.w $a0, $a0, .LCPI12_0
@@ -292,9 +290,7 @@ define double @bitcast_i64_to_double(i64 %a, i64 %b) nounwind {
; LA32-LABEL: bitcast_i64_to_double:
; LA32: # %bb.0:
; LA32-NEXT: addi.w $sp, $sp, -16
-; LA32-NEXT: addi.w $a2, $sp, 8
-; LA32-NEXT: ori $a2, $a2, 4
-; LA32-NEXT: st.w $a1, $a2, 0
+; LA32-NEXT: st.w $a1, $sp, 12
; LA32-NEXT: st.w $a0, $sp, 8
; LA32-NEXT: fld.d $fa0, $sp, 8
; LA32-NEXT: addi.w $sp, $sp, 16
@@ -313,10 +309,8 @@ define i64 @bitcast_double_to_i64(double %a) nounwind {
; LA32: # %bb.0:
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: fst.d $fa0, $sp, 8
-; LA32-NEXT: addi.w $a0, $sp, 8
-; LA32-NEXT: ori $a0, $a0, 4
-; LA32-NEXT: ld.w $a1, $a0, 0
; LA32-NEXT: ld.w $a0, $sp, 8
+; LA32-NEXT: ld.w $a1, $sp, 12
; LA32-NEXT: addi.w $sp, $sp, 16
; LA32-NEXT: jirl $zero, $ra, 0
;
diff --git a/llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll
index 30e0045a1467..167249b02617 100644
--- a/llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll
+++ b/llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll
@@ -500,10 +500,8 @@ define float @convert_u32_to_float(i32 %a) nounwind {
; LA32D-LABEL: convert_u32_to_float:
; LA32D: # %bb.0:
; LA32D-NEXT: addi.w $sp, $sp, -16
-; LA32D-NEXT: addi.w $a1, $sp, 8
-; LA32D-NEXT: ori $a1, $a1, 4
-; LA32D-NEXT: lu12i.w $a2, 275200
-; LA32D-NEXT: st.w $a2, $a1, 0
+; LA32D-NEXT: lu12i.w $a1, 275200
+; LA32D-NEXT: st.w $a1, $sp, 12
; LA32D-NEXT: st.w $a0, $sp, 8
; LA32D-NEXT: pcalau12i $a0, .LCPI14_0
; LA32D-NEXT: addi.w $a0, $a0, .LCPI14_0
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