[PATCH] D130560: [RISCV] Handle register spill in branch relaxation

Thu Jul 28 23:24:17 PDT 2022

piggynl added inline comments.

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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:1076
+  // Far branches over 20-bit offset require a spill slot for scratch register.
+  if (!isInt<20>(EstimateFunctionSizeInBytes(MF, *TII))) {
+    int FI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC),
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hiraditya wrote:
> Can we make an API like `isFarBranch` or something like it? Other places can reuse it possibly.
There is `BranchRelaxation::isBlockInRange()` in BranchRelaxation pass, but we cannot use that in PEI since there are some late optimizations between PEI and BranchRelaxation (for example MachineBlockPlacement), making us cannot determine whether a branch is a far branch or not. That's also the reason why we reserve a spill slot for BranchRelaxation pass if we estimate the function has a size over 1MiB (which means it is possible that have a branch over 1MiB).

As for an API to estimate the size of a function, it is hard to achieve in a target-independent way. (See https://reviews.llvm.org/D129975) For example, ARM places constant pools and jump tables in the middle of functions via the ConstantIslands pass while RISCV doesn't, meaning that RISCV functions never contain jumps over constant pools and jump tables. As a result, in RISCV, the size of the function does not need to include the constant pool and jump table, whereas in ARM it does.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130560/new/

https://reviews.llvm.org/D130560