[llvm] 5c38056 - [AMDGPU][Scheduler] Avoid initializing Register pressure tracker when tracking is disabled

[Anshil Gandhi via llvm-commits]

Author: Anshil Gandhi
Date: 2022-07-28T15:39:28-06:00
New Revision: 5c380564317ce90caebb2aeef44d1dbe28fb7ae6

URL: https://github.com/llvm/llvm-project/commit/5c380564317ce90caebb2aeef44d1dbe28fb7ae6
DIFF: https://github.com/llvm/llvm-project/commit/5c380564317ce90caebb2aeef44d1dbe28fb7ae6.diff

LOG: [AMDGPU][Scheduler] Avoid initializing Register pressure tracker when tracking is disabled

When register pressure tracking is disabled, the scheduler attempts to load
pressures at SReg_32 and VGPR_32. This causes an index out of bounds error.
This patch fixes this issue by disabling the initialization of RPTracker
when not needed. NFC

Reviewed By: rampitec, kerbowa, arsenm

Differential Revision: https://reviews.llvm.org/D129322

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
    llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index 7668da84fd55c..4b90513b4dede 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -79,10 +79,12 @@ void GCNMaxOccupancySchedStrategy::initCandidate(SchedCandidate &Cand, SUnit *SU
                                      const SIRegisterInfo *SRI,
                                      unsigned SGPRPressure,
                                      unsigned VGPRPressure) {
-
   Cand.SU = SU;
   Cand.AtTop = AtTop;
 
+  if (!DAG->isTrackingPressure())
+    return;
+
   // getDownwardPressure() and getUpwardPressure() make temporary changes to
   // the tracker, so we need to pass those function a non-const copy.
   RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
@@ -165,8 +167,12 @@ void GCNMaxOccupancySchedStrategy::pickNodeFromQueue(SchedBoundary &Zone,
                                          SchedCandidate &Cand) {
   const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI);
   ArrayRef<unsigned> Pressure = RPTracker.getRegSetPressureAtPos();
-  unsigned SGPRPressure = Pressure[AMDGPU::RegisterPressureSets::SReg_32];
-  unsigned VGPRPressure = Pressure[AMDGPU::RegisterPressureSets::VGPR_32];
+  unsigned SGPRPressure = 0;
+  unsigned VGPRPressure = 0;
+  if (DAG->isTrackingPressure()) {
+    SGPRPressure = Pressure[AMDGPU::RegisterPressureSets::SReg_32];
+    VGPRPressure = Pressure[AMDGPU::RegisterPressureSets::VGPR_32];
+  }
   ReadyQueue &Q = Zone.Available;
   for (SUnit *SU : Q) {
 

diff  --git a/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir b/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir
index 5cd5fbf06aa42..469a9eef4d6a5 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir
+++ b/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir
@@ -1,4 +1,6 @@
 # RUN: llc -march=amdgcn -misched=converge -run-pass machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s
+# RUN: llc -march=amdgcn -misched-regpressure=false -run-pass machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=NORP
+
 # REQUIRES: asserts
 
 # Check there is no SReg_32 pressure created by DS_* instructions because of M0 use
@@ -8,6 +10,19 @@
 # CHECK: Pressure Diff : {{$}}
 # CHECK: SU({{.*}} DS_WRITE_B32
 
+# NORP: ScheduleDAGMILive::schedule starting
+# NORP: GenericScheduler RegionPolicy:  ShouldTrackPressure=0
+# NORP-NOT: Pressure Diff : {{$}}
+# NORP-NOT: Pressure Diff : {{$}}
+# NORP-NOT: Pressure Diff : {{$}}
+# NORP-NOT: Pressure Diff : {{$}}
+# NORP-NOT: Pressure Diff : {{$}}
+# NORP-NOT: Pressure Diff : {{$}}
+# NORP-NOT: Bottom Pressure:
+# NORP-NOT: UpdateRegP
+# NORP-NOT: UpdateRegP
+# NORP-NOT: UpdateRegP
+
 ---
 name:            mo_pset
 alignment:       1