[PATCH] D130677: [AMDGPU] Fix DGEMM hazard for GFX90a

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPU.td:282
 
+def FeatureDGEMMVALUWriteMemOpBug : SubtargetFeature<"dgemm-valu-write-mem-op-bug",
+  "HasDGEMMVALUWriteMemOpBug",
----------------
vangthao wrote:
> rampitec wrote:
> > kerbowa wrote:
> > > vangthao wrote:
> > > > rampitec wrote:
> > > > > I do not believe it deserves a feature bit. These bits are limited.
> > > > Is there a way to check for gfx90a only? I thought about `hasGFX90AInsts()` but this also includes gfx940. We could exclude gfx940 with `!hasGFX940Insts()` but that does not seem like a clean way of doing so.
> > > Isn't the max number of bits 256? So we are at 143/256? Do we have a good way of checking for a specific processor beyond adding feature bits for each one?
> > Right. Imagine we are using a bit for every HW bug. In this case a check would be `hasGFX90Insts() && !hasGFX940Insts()`.
> Can we use `AMDGPU::IsaVersion` to check for gfx90a or would `hasGFX90AInsts() && !hasGFX940Insts()` be better? The latter does not seem future proof if more subtargets would be added that include gfx90a but not gfx940.
Either way works.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D130677/new/

https://reviews.llvm.org/D130677