[PATCH] D130677: [AMDGPU] Fix DGEMM hazard for GFX90a

[Vang Thao via Phabricator via llvm-commits]

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For VALU write and memory (VM, L/DS, FLAT) instructions, SQ would insert
wait-states to avoid data hazard. However when there is a DGEMM instruction
in-between them, SQ incorrectly disables the wait-states thus the data hazard
needs to be handled with this workaround.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D130677

Files:
  llvm/lib/Target/AMDGPU/AMDGPU.td
  llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  llvm/lib/Target/AMDGPU/GCNSubtarget.h
  llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
  llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir

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