[llvm] 06da353 - [NFC] Automatically generate CodeGen/VE/Scalar/atomic.ll
Amaury Séchet via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 27 16:54:28 PDT 2022
Author: Amaury Séchet
Date: 2022-07-27T23:52:00Z
New Revision: 06da353748c967f57c357a97b95643bd9c172e71
URL: https://github.com/llvm/llvm-project/commit/06da353748c967f57c357a97b95643bd9c172e71
DIFF: https://github.com/llvm/llvm-project/commit/06da353748c967f57c357a97b95643bd9c172e71.diff
LOG: [NFC] Automatically generate CodeGen/VE/Scalar/atomic.ll
Added:
Modified:
llvm/test/CodeGen/VE/Scalar/atomic.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/VE/Scalar/atomic.ll b/llvm/test/CodeGen/VE/Scalar/atomic.ll
index 46c0f8f95887..f01bf0ff66c3 100644
--- a/llvm/test/CodeGen/VE/Scalar/atomic.ll
+++ b/llvm/test/CodeGen/VE/Scalar/atomic.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
;;; Test atomicrmw operations
@@ -19,7 +20,7 @@ define signext i8 @test_atomic_fetch_add_1() {
; CHECK-NEXT: ldl.sx %s2, (, %s0)
; CHECK-NEXT: lea %s1, -256
; CHECK-NEXT: and %s1, %s1, (32)0
-; CHECK-NEXT: .LBB{{[0-9]+}}_1: # %atomicrmw.start
+; CHECK-NEXT: .LBB0_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s3, 0, %s2
; CHECK-NEXT: adds.w.sx %s2, 1, %s2
@@ -27,7 +28,7 @@ define signext i8 @test_atomic_fetch_add_1() {
; CHECK-NEXT: and %s4, %s3, %s1
; CHECK-NEXT: or %s2, %s4, %s2
; CHECK-NEXT: cas.w %s2, (%s0), %s3
-; CHECK-NEXT: brne.w %s2, %s3, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: brne.w %s2, %s3, .LBB0_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: sll %s0, %s2, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
@@ -50,7 +51,7 @@ define signext i16 @test_atomic_fetch_sub_2() {
; CHECK-NEXT: ldl.sx %s2, (, %s0)
; CHECK-NEXT: lea %s1, -65536
; CHECK-NEXT: and %s1, %s1, (32)0
-; CHECK-NEXT: .LBB{{[0-9]+}}_1: # %atomicrmw.start
+; CHECK-NEXT: .LBB1_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s3, 0, %s2
; CHECK-NEXT: adds.w.sx %s2, -1, %s2
@@ -58,7 +59,7 @@ define signext i16 @test_atomic_fetch_sub_2() {
; CHECK-NEXT: and %s4, %s3, %s1
; CHECK-NEXT: or %s2, %s4, %s2
; CHECK-NEXT: cas.w %s2, (%s0), %s3
-; CHECK-NEXT: brne.w %s2, %s3, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: brne.w %s2, %s3, .LBB1_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: sll %s0, %s2, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
@@ -78,12 +79,12 @@ define signext i32 @test_atomic_fetch_and_4() {
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, i at hi(, %s0)
; CHECK-NEXT: ldl.sx %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_1: # %atomicrmw.start
+; CHECK-NEXT: .LBB2_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s2, 0, %s1
; CHECK-NEXT: and %s1, 1, %s2
; CHECK-NEXT: cas.w %s1, (%s0), %s2
-; CHECK-NEXT: brne.w %s1, %s2, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: brne.w %s1, %s2, .LBB2_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: fencem 3
@@ -101,12 +102,12 @@ define i64 @test_atomic_fetch_or_8() {
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s1, l at hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_1: # %atomicrmw.start
+; CHECK-NEXT: .LBB3_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s2, 0, %s0
; CHECK-NEXT: or %s0, 1, %s0
; CHECK-NEXT: cas.l %s0, (%s1), %s2
-; CHECK-NEXT: brne.l %s0, %s2, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: brne.l %s0, %s2, .LBB3_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: fencem 3
; CHECK-NEXT: b.l.t (, %s10)
@@ -125,12 +126,12 @@ define signext i8 @test_atomic_fetch_xor_1() {
; CHECK-NEXT: lea.sl %s0, c at hi(, %s0)
; CHECK-NEXT: and %s1, -4, %s0
; CHECK-NEXT: ldl.sx %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_1: # %atomicrmw.start
+; CHECK-NEXT: .LBB4_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s2, 0, %s0
; CHECK-NEXT: xor %s0, 1, %s2
; CHECK-NEXT: cas.w %s0, (%s1), %s2
-; CHECK-NEXT: brne.w %s0, %s2, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: brne.w %s0, %s2, .LBB4_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
@@ -154,7 +155,7 @@ define signext i16 @test_atomic_fetch_nand_2() {
; CHECK-NEXT: lea %s1, 65534
; CHECK-NEXT: lea %s3, -65536
; CHECK-NEXT: and %s3, %s3, (32)0
-; CHECK-NEXT: .LBB{{[0-9]+}}_1: # %atomicrmw.start
+; CHECK-NEXT: .LBB5_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s4, 0, %s2
; CHECK-NEXT: xor %s2, -1, %s4
@@ -163,7 +164,7 @@ define signext i16 @test_atomic_fetch_nand_2() {
; CHECK-NEXT: and %s5, %s4, %s3
; CHECK-NEXT: or %s2, %s5, %s2
; CHECK-NEXT: cas.w %s2, (%s0), %s4
-; CHECK-NEXT: brne.w %s2, %s4, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: brne.w %s2, %s4, .LBB5_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: sll %s0, %s2, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
@@ -184,12 +185,12 @@ define signext i32 @test_atomic_fetch_max_4() {
; CHECK-NEXT: lea.sl %s1, i at hi(, %s0)
; CHECK-NEXT: ldl.sx %s0, (, %s1)
; CHECK-NEXT: or %s2, 1, (0)1
-; CHECK-NEXT: .LBB{{[0-9]+}}_1: # %atomicrmw.start
+; CHECK-NEXT: .LBB6_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s3, 0, %s0
; CHECK-NEXT: maxs.w.sx %s0, %s0, %s2
; CHECK-NEXT: cas.w %s0, (%s1), %s3
-; CHECK-NEXT: brne.w %s0, %s3, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: brne.w %s0, %s3, .LBB6_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: fencem 3
@@ -209,14 +210,14 @@ define signext i32 @test_atomic_fetch_min_4() {
; CHECK-NEXT: lea.sl %s0, i at hi(, %s0)
; CHECK-NEXT: ldl.sx %s1, (, %s0)
; CHECK-NEXT: or %s2, 2, (0)1
-; CHECK-NEXT: .LBB{{[0-9]+}}_1: # %atomicrmw.start
+; CHECK-NEXT: .LBB7_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s3, 0, %s1
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s2
; CHECK-NEXT: or %s1, 1, (0)1
; CHECK-NEXT: cmov.w.lt %s1, %s3, %s4
; CHECK-NEXT: cas.w %s1, (%s0), %s3
-; CHECK-NEXT: brne.w %s1, %s3, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: brne.w %s1, %s3, .LBB7_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: fencem 3
@@ -236,14 +237,14 @@ define signext i32 @test_atomic_fetch_umax_4() {
; CHECK-NEXT: lea.sl %s0, i at hi(, %s0)
; CHECK-NEXT: ldl.sx %s1, (, %s0)
; CHECK-NEXT: or %s2, 1, (0)1
-; CHECK-NEXT: .LBB{{[0-9]+}}_1: # %atomicrmw.start
+; CHECK-NEXT: .LBB8_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s3, 0, %s1
; CHECK-NEXT: cmpu.w %s4, %s1, %s2
; CHECK-NEXT: or %s1, 1, (0)1
; CHECK-NEXT: cmov.w.gt %s1, %s3, %s4
; CHECK-NEXT: cas.w %s1, (%s0), %s3
-; CHECK-NEXT: brne.w %s1, %s3, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: brne.w %s1, %s3, .LBB8_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: fencem 3
@@ -263,14 +264,14 @@ define signext i32 @test_atomic_fetch_umin_4() {
; CHECK-NEXT: lea.sl %s0, i at hi(, %s0)
; CHECK-NEXT: ldl.sx %s1, (, %s0)
; CHECK-NEXT: or %s2, 2, (0)1
-; CHECK-NEXT: .LBB{{[0-9]+}}_1: # %atomicrmw.start
+; CHECK-NEXT: .LBB9_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s3, 0, %s1
; CHECK-NEXT: cmpu.w %s4, %s1, %s2
; CHECK-NEXT: or %s1, 1, (0)1
; CHECK-NEXT: cmov.w.lt %s1, %s3, %s4
; CHECK-NEXT: cas.w %s1, (%s0), %s3
-; CHECK-NEXT: brne.w %s1, %s3, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: brne.w %s1, %s3, .LBB9_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: fencem 3
More information about the llvm-commits
mailing list