[llvm] 1a6d82b - Fix misc uses of "long" variables to use "int64_t".
Eli Friedman via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 27 09:47:55 PDT 2022
Author: Eli Friedman
Date: 2022-07-27T09:47:19-07:00
New Revision: 1a6d82b93f6b9101f62238f112f92b07877b8c21
URL: https://github.com/llvm/llvm-project/commit/1a6d82b93f6b9101f62238f112f92b07877b8c21
DIFF: https://github.com/llvm/llvm-project/commit/1a6d82b93f6b9101f62238f112f92b07877b8c21.diff
LOG: Fix misc uses of "long" variables to use "int64_t".
I don't have any evidence these particular uses are actually causing any
issues, but we should avoid accidentally truncating immediate values
depending on the host.
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
llvm/lib/Target/PowerPC/PPCFastISel.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 2a9393fc15957..effde63adc3d8 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -3865,7 +3865,7 @@ bool AMDGPUAsmParser::validateMIMGDim(const MCInst &Inst) {
if (DimIdx < 0)
return true;
- long Imm = Inst.getOperand(DimIdx).getImm();
+ int64_t Imm = Inst.getOperand(DimIdx).getImm();
if (Imm < 0 || Imm >= 8)
return false;
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index cf311337d5eba..781f1097176d4 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -177,7 +177,7 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS,
LowerCompactBranch(TmpInst);
}
- unsigned long N = Fixups.size();
+ size_t N = Fixups.size();
uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
// Check for unimplemented opcodes.
diff --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
index 7b1b9456080e8..bfdbdcb0254e5 100644
--- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
@@ -74,7 +74,7 @@ struct Address {
int FI;
} Base;
- long Offset;
+ int64_t Offset;
// Innocuous defaults for our address.
Address()
@@ -338,7 +338,7 @@ bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
break;
case Instruction::GetElementPtr: {
Address SavedAddr = Addr;
- long TmpOffset = Addr.Offset;
+ int64_t TmpOffset = Addr.Offset;
// Iterate through the GEP folding the constants into offsets where
// we can.
@@ -437,8 +437,7 @@ void PPCFastISel::PPCSimplifyAddress(Address &Addr, bool &UseOffset,
if (!UseOffset) {
IntegerType *OffsetTy = Type::getInt64Ty(*Context);
- const ConstantInt *Offset =
- ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
+ const ConstantInt *Offset = ConstantInt::getSigned(OffsetTy, Addr.Offset);
IndexReg = PPCMaterializeInt(Offset, MVT::i64);
assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
}
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 3c461a627d61c..5feeb55e2ddd5 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15415,7 +15415,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
MachineFunction &MF = DAG.getMachineFunction();
MachineMemOperand *BaseMMO =
MF.getMachineMemOperand(LD->getMemOperand(),
- -(long)MemVT.getStoreSize()+1,
+ -(int64_t)MemVT.getStoreSize()+1,
2*MemVT.getStoreSize()-1);
// Create the new base load.
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index f651b51d26845..88d3290f6c333 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -478,7 +478,7 @@ def HI16 : SDNodeXForm<imm, [{
def HA16 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
- long Val = N->getZExtValue();
+ int64_t Val = N->getZExtValue();
return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
}]>;
def MB : SDNodeXForm<imm, [{
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