[llvm] 9b27d13 - [RISCV] Disable constant hoisting for multiply by negated power of 2.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-07-27T09:37:59-07:00
New Revision: 9b27d13204969bfb57ef408ec2c95e5b1f63fc43

URL: https://github.com/llvm/llvm-project/commit/9b27d13204969bfb57ef408ec2c95e5b1f63fc43
DIFF: https://github.com/llvm/llvm-project/commit/9b27d13204969bfb57ef408ec2c95e5b1f63fc43.diff

LOG: [RISCV] Disable constant hoisting for multiply by negated power of 2.

A mul by a negated power of 2 is a slli followed by neg. This doesn't
require any constant materialization and may be lower latency than mul.
The neg may also be foldable into other arithmetic.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D130047

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index f9cd5ffb512ba..cea2fb934cf51 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -71,7 +71,13 @@ InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
   case Instruction::Add:
   case Instruction::Or:
   case Instruction::Xor:
+    Takes12BitImm = true;
+    break;
   case Instruction::Mul:
+    // Negated power of 2 is a shift and a negate.
+    if (Imm.isNegatedPowerOf2())
+      return TTI::TCC_Free;
+    // FIXME: There is no MULI instruction.
     Takes12BitImm = true;
     break;
   case Instruction::Sub:

diff  --git a/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll b/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
index 92441afa94018..e1badcb3545dd 100644
--- a/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
+++ b/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
@@ -72,3 +72,12 @@ define i64 @test8(i64 %a) nounwind "target-features"="+zba" {
   %2 = and i64 %1, 4294967295
   ret i64 %2
 }
+
+; Check that we don't hoist mul with negated power of 2.
+define i64 @test9(i64 %a) nounwind {
+; CHECK-LABEL: test9
+; CHECK: mul i64 %a, -4294967296
+  %1 = mul i64 %a, -4294967296
+  %2 = mul i64 %1, -4294967296
+  ret i64 %2
+}