[PATCH] D130634: [AMDGPU][MC][GFX11] Disable SGPRs for src1 of v_fma_mix*_dpp opcodes
Dmitry Preobrazhensky via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 27 07:19:03 PDT 2022
dp created this revision.
dp added reviewers: Joe_Nash, foad.
Herald added subscribers: kosarev, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, jvesely, kzhuravl, arsenm.
Herald added a project: All.
dp requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.
See bug 56735 <https://github.com/llvm/llvm-project/issues/56735>.
https://reviews.llvm.org/D130634
Files:
llvm/lib/Target/AMDGPU/VOP3PInstructions.td
llvm/test/MC/AMDGPU/gfx11_err.s
Index: llvm/test/MC/AMDGPU/gfx11_err.s
===================================================================
--- llvm/test/MC/AMDGPU/gfx11_err.s
+++ llvm/test/MC/AMDGPU/gfx11_err.s
@@ -77,3 +77,21 @@
v_dot4c_i32_i8 v0, v1, v2
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+v_fma_mix_f32_e64_dpp v5, s1, v3, v4 quad_perm:[3,2,1,0]
+// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_fma_mix_f32_e64_dpp v5, v1, s3, v4 quad_perm:[3,2,1,0]
+// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_fma_mix_f32_e64_dpp v5, s1, v3, v4 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_fma_mix_f32_e64_dpp v5, v1, s3, v4 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_fma_mixhi_f16_e64_dpp v5, v1, 0, v4 quad_perm:[3,2,1,0]
+// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_fma_mixlo_f16_e64_dpp v5, v1, 1, v4 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
Index: llvm/lib/Target/AMDGPU/VOP3PInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -35,7 +35,7 @@
FP16InputMods:$src2_modifiers, VCSrc_f16:$src2);
dag dpp_srcs =
(ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0,
- FP16InputMods:$src1_modifiers, VCSrc_f16:$src1,
+ FPVRegInputMods:$src1_modifiers, VGPRSrc_32:$src1,
FP16InputMods:$src2_modifiers, VCSrc_f16:$src2);
// FIXME: clampmod0 misbehaves with the non-default vdst_in
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