[PATCH] D130610: [RISCV] Reorder (and/or/xor (shl X, C1), C2) if we can form ANDI/ORI/XORI.

[Craig Topper via Phabricator via llvm-commits]

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InstCombine and DAGCombine prefer to keep shl before binops.

This patch teaches isel to convert to (shl (and/or/xor X, C1 <https://reviews.llvm.org/C1> >> C2), C2)
if (C1 <https://reviews.llvm.org/C1> >> C2) is a simm12. The idea was taken from X86's isel code.

There's a special case implemented for a sext_inreg between the
shift and the binop.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D130610

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/test/CodeGen/RISCV/narrow-shl-cst.ll

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