[PATCH] D130548: [AArch64] Explicitly use v1i64 type for llvm.aarch64.neon.pmull64

[Mingming Liu via Phabricator via llvm-commits]

mingmingl added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4523
+    SDValue Op2 = Op.getOperand(2);
+    if (Op1.getNode()->getOpcode() == ISD::LOAD &&
+        Op1.getNode()->getValueType(0) == MVT::i64) {
----------------
dmgreen wrote:
> Can we do this for all operands, not just loads? We should end up adding the i64->v1i64 copy in either case.
Generalize by doing this for all operands, except when they are higher half of the SIMD register, and added comments to explain why.
- When operands are higher half, this [[ https://github.com/llvm/llvm-project/blob/3928e89c319920d053500cbccf0093589bb041a8/llvm/lib/Target/AArch64/AArch64InstrInfo.td#L5302 | tablegen pattern ]] is optimal -> [[ https://github.com/llvm/llvm-project/blob/6d0b42745e55c703b779740f5316adbac8ef2f25/llvm/test/CodeGen/AArch64/arm64-vmul.ll#L2936 | test_pmull_high_64 ]] shows this.

Also add test2 and test3 for this generalization
- https://gcc.godbolt.org/z/79sajTcf7 is codegen of trunk
- test2 has a load and an extract-element
- test3 has a load and a direct use of i64

Also I'd be glad to send an NFC patch of the test case first, and the diffs become more obvious with this patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130548/new/

https://reviews.llvm.org/D130548