[llvm] 39d431d - [GlobalISel] Import patterns for G_FMAXIMUM + G_FMINIMUM
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 26 10:59:21 PDT 2022
Author: Jessica Paquette
Date: 2022-07-26T10:58:44-07:00
New Revision: 39d431d81132f9334ed10477e94d9b2f3c9f788d
URL: https://github.com/llvm/llvm-project/commit/39d431d81132f9334ed10477e94d9b2f3c9f788d
DIFF: https://github.com/llvm/llvm-project/commit/39d431d81132f9334ed10477e94d9b2f3c9f788d.diff
LOG: [GlobalISel] Import patterns for G_FMAXIMUM + G_FMINIMUM
Allows us to select scalar instructions on AArch64.
Differential Revision: https://reviews.llvm.org/D115381
Added:
llvm/test/CodeGen/AArch64/GlobalISel/select-fmaximum.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-fminimum.mir
Modified:
llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
Removed:
################################################################################
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index ef4fc85b245de..5b8b852962f48 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -141,6 +141,8 @@ def : GINodeEquiv<G_FMINNUM, fminnum>;
def : GINodeEquiv<G_FMAXNUM, fmaxnum>;
def : GINodeEquiv<G_FMINNUM_IEEE, fminnum_ieee>;
def : GINodeEquiv<G_FMAXNUM_IEEE, fmaxnum_ieee>;
+def : GINodeEquiv<G_FMAXIMUM, fmaximum>;
+def : GINodeEquiv<G_FMINIMUM, fminimum>;
def : GINodeEquiv<G_READCYCLECOUNTER, readcyclecounter>;
def : GINodeEquiv<G_ROTR, rotr>;
def : GINodeEquiv<G_ROTL, rotl>;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fmaximum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fmaximum.mir
new file mode 100644
index 0000000000000..481d0f1d6b9c4
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fmaximum.mir
@@ -0,0 +1,74 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+...
+---
+name: s16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $h0, $h1
+
+ ; CHECK-LABEL: name: s16
+ ; CHECK: liveins: $h0, $h1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:fpr16 = COPY $h0
+ ; CHECK-NEXT: %b:fpr16 = COPY $h1
+ ; CHECK-NEXT: %select_me:fpr16 = nofpexcept FMAXHrr %a, %b
+ ; CHECK-NEXT: $h0 = COPY %select_me
+ ; CHECK-NEXT: RET_ReallyLR implicit $h0
+ %a:fpr(s16) = COPY $h0
+ %b:fpr(s16) = COPY $h1
+ %select_me:fpr(s16) = G_FMAXIMUM %a, %b
+ $h0 = COPY %select_me(s16)
+ RET_ReallyLR implicit $h0
+
+...
+---
+name: s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $s0, $s1
+
+ ; CHECK-LABEL: name: s32
+ ; CHECK: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:fpr32 = COPY $s0
+ ; CHECK-NEXT: %b:fpr32 = COPY $s1
+ ; CHECK-NEXT: %select_me:fpr32 = nofpexcept FMAXSrr %a, %b
+ ; CHECK-NEXT: $s0 = COPY %select_me
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ %a:fpr(s32) = COPY $s0
+ %b:fpr(s32) = COPY $s1
+ %select_me:fpr(s32) = G_FMAXIMUM %a, %b
+ $s0 = COPY %select_me(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $d0, $d1
+
+ ; CHECK-LABEL: name: s64
+ ; CHECK: liveins: $d0, $d1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:fpr64 = COPY $d0
+ ; CHECK-NEXT: %b:fpr64 = COPY $d1
+ ; CHECK-NEXT: %select_me:fpr64 = nofpexcept FMAXDrr %a, %b
+ ; CHECK-NEXT: $d0 = COPY %select_me
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %a:fpr(s64) = COPY $d0
+ %b:fpr(s64) = COPY $d1
+ %select_me:fpr(s64) = G_FMAXIMUM %a, %b
+ $d0 = COPY %select_me(s64)
+ RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fminimum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fminimum.mir
new file mode 100644
index 0000000000000..5ffda6d557a28
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fminimum.mir
@@ -0,0 +1,74 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+...
+---
+name: s16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $h0, $h1
+
+ ; CHECK-LABEL: name: s16
+ ; CHECK: liveins: $h0, $h1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:fpr16 = COPY $h0
+ ; CHECK-NEXT: %b:fpr16 = COPY $h1
+ ; CHECK-NEXT: %select_me:fpr16 = nofpexcept FMINHrr %a, %b
+ ; CHECK-NEXT: $h0 = COPY %select_me
+ ; CHECK-NEXT: RET_ReallyLR implicit $h0
+ %a:fpr(s16) = COPY $h0
+ %b:fpr(s16) = COPY $h1
+ %select_me:fpr(s16) = G_FMINIMUM %a, %b
+ $h0 = COPY %select_me(s16)
+ RET_ReallyLR implicit $h0
+
+...
+---
+name: s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $s0, $s1
+
+ ; CHECK-LABEL: name: s32
+ ; CHECK: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:fpr32 = COPY $s0
+ ; CHECK-NEXT: %b:fpr32 = COPY $s1
+ ; CHECK-NEXT: %select_me:fpr32 = nofpexcept FMINSrr %a, %b
+ ; CHECK-NEXT: $s0 = COPY %select_me
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ %a:fpr(s32) = COPY $s0
+ %b:fpr(s32) = COPY $s1
+ %select_me:fpr(s32) = G_FMINIMUM %a, %b
+ $s0 = COPY %select_me(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $d0, $d1
+
+ ; CHECK-LABEL: name: s64
+ ; CHECK: liveins: $d0, $d1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:fpr64 = COPY $d0
+ ; CHECK-NEXT: %b:fpr64 = COPY $d1
+ ; CHECK-NEXT: %select_me:fpr64 = nofpexcept FMINDrr %a, %b
+ ; CHECK-NEXT: $d0 = COPY %select_me
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %a:fpr(s64) = COPY $d0
+ %b:fpr(s64) = COPY $d1
+ %select_me:fpr(s64) = G_FMINIMUM %a, %b
+ $d0 = COPY %select_me(s64)
+ RET_ReallyLR implicit $d0
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